K4S511633C SAMSUNG [Samsung semiconductor], K4S511633C Datasheet - Page 2

• Manufacturer Part Number: K4S511633C
• Description: 32Mx16 Mobile SDRAM 54CSP 1/CS
• Manufacturer: SAMSUNG [Samsung semiconductor]

K4S511633C-YL/N/P
8M x 16Bit x 4 Banks Mobile SDRAM
FEATURES
• 3.0V power supply
• LVCMOS compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
• All inputs are sampled at the positive going edge of the system
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K cycle)
• 1 /CS Support.
• Commercial Temperature Operation (-25 C ~ 70 C).
• 54balls DDP CSP
FUNCTIONAL BLOCK DIAGRAM
clock.
Extended Temperature Operation (-25 C ~ 85 C).
Industrial Temperature Operation (-40 C ~ 85 C).
-. Burst length (1, 2, 4, 8 & Full page)
-. CAS latency (1 & 2 & 3)
-. Burst type (Sequential & Interleave)
CLK
ADD
LCKE
CLK
LRAS
CKE
Bank Select
LCBR
CS
LWE
RAS
Timing Register
LCAS
CAS
ORDERING INFORMATION
- YN : Low Power, Operating Temp : -25 C ~ 85 C.
- YL : Low Power, Operating Temp : -25 C ~ 70 C.
- YP : Low Power, Operating Temp : -40 C ~ 85 C.
Note :
1. In case of 33MHz Frequency, CL1 can be supported.
GENERAL DESCRIPTION
rate Dynamic RAM organized as 4 x 8,388,608 words by 16bits,
fabricated with SAMSUNG's high performance CMOS technology.
Synchronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
K4S511633C-YL/N1H
Latency & Burst Length
K4S511633C-YL/N80
K4S511633C-YL/N1L
Programming Register
WE
The K4S511633C is 536,870,912 bits synchronous high data
Data Input Register
Column Decoder
8M x 16
8M x 16
8M x 16
8M x 16
Part No.
DQM
LWCBR
*
Samsung Electronics reserves the right to
change products or specification without
notice.
100MHz(CL=3)
125MHz(CL=3)
100MHz(CL=2)
100MHz(CL=2)
Max Freq.
CMOS SDRAM
Rev. 1.2 Dec. 2002
*1
LDQM
Interface
LVCMOS
LWE
LDQM
DQi
Package
54 CSP