K9F1208B0B SAMSUNG [Samsung semiconductor], K9F1208B0B Datasheet

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K9F1208B0B

Manufacturer Part Number
K9F1208B0B
Description
64M x 8 Bit NAND Flash Memory
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet

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K9F1208B0B-JIB0
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K9F1208R0B
K9F1208B0B
K9F1208U0B
Document Title
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
Revision History
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
Revision No.
64M x 8 Bit NAND Flash Memory
http://www.samsung.com/Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm
0.0
0.1
History
Initial issue.
1. Note 1 ( Program/Erase Characteristics) is added( page 14 )
2. NAND Flash Technical Notes is changed.
3. Vcc range is changed
4
device.
. Multi plane operation and Copy-Back Program are not supported with 1.8V
-Invalid block -> initial invalid block ( page 16 )
-Error in write or read operation ( page 17 )
-Program Flow Chart ( page 17 )
-2.4V~2.9V -> 2.5V~2.9V
-1.7V~1.95V ->1.65V~1.95V
1
Draft Date
Apr. 24th 2004
Oct. 11th.2004
FLASH MEMORY
Preliminary
Remark
Advance
Preliminary

Related parts for K9F1208B0B

K9F1208B0B Summary of contents

Page 1

... K9F1208R0B K9F1208B0B K9F1208U0B Document Title 64M x 8 Bit NAND Flash Memory Revision History Revision No. History 0.0 Initial issue. 0.1 1. Note 1 ( Program/Erase Characteristics) is added( page NAND Flash Technical Notes is changed. -Invalid block -> initial invalid block ( page 16 ) -Error in write or read operation ( page 17 ) -Program Flow Chart ( page Vcc range is changed -2.4V~2.9V -> ...

Page 2

... K9F1208B0B-G,J K9F1208U0B-Y,P 2.7 ~ 3.6V K9F1208U0B-G,J K9F1208U0B-V,F FEATURES • Voltage Supply - 1.8V device(K9F1208R0B) : 1.65~1.95V - 2.7V device(K9F1208B0B) : 2.5~2.9V - 3.3V device(K9F1208U0B) : 2.7 ~ 3.6 V • Organization - Memory Cell Array : (64M + 2048K)bit x 8 bit - Data Register : (512 + 16)bit x 8bit • Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (16K + 512)Byte • Page Read Operation ...

Page 3

... K9F1208R0B K9F1208B0B K9F1208U0B PIN CONFIGURATION (TSOP1) K9F1208U0B-YCB0,PCB0/YIB0,PIB0 N.C 1 N.C 2 N.C 3 N.C 4 N.C 5 N N.C 10 N.C 11 Vcc 12 Vss 13 N.C 14 N.C 15 CLE 16 ALE N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 0~8° 0.45~0.75 0.018~0.030 48 47 ...

Page 4

Package Dimensions PIN CONFIGURATION (WSOP1) K9F1208U0B-VCB0,FCB0/VIB0,FIB0 N.C 1 N.C 2 DNU 3 N.C 4 N.C 5 N DNU 10 N.C 11 Vcc 12 Vss 13 N.C 14 DNU 15 CLE 16 ALE 17 ...

Page 5

... K9F1208R0B K9F1208B0B K9F1208U0B PIN CONFIGURATION (FBGA) K9F1208X0B-GCB0,JCB0/GIB0,JIB0 N.C N.C N N.C N.C N N.C N.C N.C N.C /WP ALE Vss /CE /WE R/B NC /RE CLE I/ Vcc NC I/O1 NC VccQ I/O5 I/O7 Vss I/O2 I/O3 I/O4 I/O6 Vss N.C N.C N.C N.C N.C Top View 5 Preliminary FLASH MEMORY ...

Page 6

Package Dimensions 63-Ball FBGA (measured in millimeters) Top View 8.50 ±0.10 #A1 0.10MAX FLASH MEMORY Bottom View 8.50 ±0.10 0. 7.20 0. 4.00 0. (Datum (Datum ...

Page 7

... K9F1208R0B K9F1208B0B K9F1208U0B PIN DESCRIPTION Pin Name I/O ~ I/O DATA INPUTS/OUTPUTS 0 7 (K9F1208X0B) The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register ...

Page 8

... K9F1208R0B K9F1208B0B K9F1208U0B Figure 1-1. K9F1208X0B FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-1. K9F1208X0B ARRAY ORGANIZATION 128K Pages 1st half Page Register ...

Page 9

... K9F1208R0B K9F1208B0B K9F1208U0B Product Introduction The K9F1208X0B is a 528Mbit(553,648,218 bit) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...

Page 10

... K9F1208R0B K9F1208B0B K9F1208U0B Memory Map The device is arranged in four 128Mbit memory planes. Each plane contains 1,024 blocks and 528 byte page registers. This allows it to perform simultaneous page program and block erase by selecting one page or block from each plane. The block address map is configured so that multi-plane program/erase operations can be executed for every four sequential blocks ...

Page 11

... IN/OUT 2.45 CCQ -10 to +125 T BIAS -40 to +125 T -65 to +150 STG Ios +0.3V which, during transitions, may overshoot 70°C, K9F1208X0B-XIB0 T =-40 to 85° K9F1208B0B(2.7V) Typ. Max Min Typ. Max 1.8 1.95 2.5 2.7 2.9 1.8 1.95 2.5 2.7 2 Preliminary FLASH MEMORY Rating Unit 3 ...

Page 12

... K9F1208B0B :I OH K9F1208U0B :I K9F1208R0B :I Output Low Voltage Level V K9F1208B0B :I OL K9F1208U0B :I K9F1208R0B :V Output Low Current(R/B) I (R/B) K9F1208B0B :V OL K9F1208U0B :V NOTE : VIL can undershoot to -0.4V and VIH can overshoot to VCC +0.4V for durations less. (Recommended operating conditions otherwise noted.) K9F1208X0B 1.8V Min Typ Max Min - 8 ...

Page 13

... Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space. AC TEST CONDITION (K9F1208X0B-XCB0 :TA=0 to 70°C, K9F1208X0B-XIB0:TA=-40 to 85°C K9F1208R0B : Vcc=1.65V~1.95V , K9F1208B0B : Vcc=2.5V~2.9V , K9F1208U0B : Vcc=2.7V~3.6V unless otherwise noted) Parameter Input Pulse Levels Input Rise and Fall Times ...

Page 14

... K9F1208R0B K9F1208B0B K9F1208U0B PROGRAM / ERASE CHARACTERISTICS Parameter Program Time Dummy Busy Time for Multi Plane Program Number of Partial Program Cycles in the Same Page Block Erase Time NOTE : 1.Typical program time is defined as the time within more than 50% of the whole pages are programmed at Vcc of 3.3V and 25’C ...

Page 15

... K9F1208R0B K9F1208B0B K9F1208U0B AC CHARACTERISTICS FOR OPERATION Parameter Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time CE Access Time RE High to Output Hi-Z CE High to Output Hi High to Output hold RE High Hold Time ...

Page 16

... K9F1208R0B K9F1208B0B K9F1208U0B NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block( called as the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...

Page 17

... K9F1208R0B K9F1208B0B K9F1208U0B NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block failure rete.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done ...

Page 18

... K9F1208R0B K9F1208B0B K9F1208U0B NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. ...

Page 19

... K9F1208R0B K9F1208B0B K9F1208U0B Pointer Operation of K9F1208X0B Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’ command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets the pointer to ’ ...

Page 20

... K9F1208R0B K9F1208B0B K9F1208U0B System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption ...

Page 21

... K9F1208R0B K9F1208B0B K9F1208U0B Device K9F1208X0B Command Latch Cycle CLE t CLS ALS ALE I/O X Address Latch Cycle t CLS CLE ALS ALE t I/O X I/O I/ CLH ALH Command ALH ...

Page 22

... K9F1208R0B K9F1208B0B K9F1208U0B Input Data Latch Cycle CLE ALS WC ALE I/Ox DIN 0 Serial access Cycle after Read CE t REA RE I/ R/B NOTES : Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested ...

Page 23

... K9F1208R0B K9F1208B0B K9F1208U0B Status Read Cycle CLE t CLS I/O X READ1 OPERATION (READ ONE PAGE) CLE ALE RE N Address I/O 00h or 01h Column Page(Row) Address Address R/B X8 device : m = 528 , Read CMD = 00h or 01h t CLR t CLH ...

Page 24

... K9F1208R0B K9F1208B0B K9F1208U0B Read1 Operation (Intercepted by CE) CLE CE WE ALE I/O 00h or 01h Column Address R/B Read2 Operation (Read One Page) CLE CE WE ALE RE I/O 50h R/B M Address K9F1208X0B-Y,P or K9F1208X0B-V,F CE must be held low during tR ...

Page 25

... K9F1208R0B K9F1208B0B K9F1208U0B Sequential Row Read Operation CLE CE WE ALE RE 00h I R/B M Page Program Operation CLE ALE RE I/O 80h Sequential Data Column Page(Row) Input Command Address R/B (Within a Block) Dout Dout ~ ...

Page 26

... K9F1208R0B K9F1208B0B K9F1208U0B BLOCK ERASE OPERATION (ERASE ONE BLOCK) CLE ALE RE I/O 60h Page(Row) Address R/B Auto Block Erase Setup Command t t BERS WB DOh A 25 Busy Erase Command 26 Preliminary FLASH MEMORY 70h I/O 0 I/O =0 Successful Erase 0 Read Status ...

Page 27

... K9F1208R0B K9F1208B0B K9F1208U0B ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ ≈ 27 Preliminary FLASH MEMORY ...

Page 28

... K9F1208R0B K9F1208B0B K9F1208U0B Multi-Plane Block Erase Operation CLE ALE RE I/O 60h Page(Row) Address R/B Block Erase Setup Command Max. 4 times repeatable * For Multi-Plane Erase operation, Block address to be erased should be repeated before "D0H" command. Ex.) Four-Plane Block Erase Operation ...

Page 29

... Must be don’t -cared 3 rd Byte Supports Multi Plane Operation 4 Byte th (Must be don’t-cared for 1.8 device) t REA Device 00h ECh Code Maker Code Device K9F1208R0B K9F1208B0B K9F1208U0B 29 Preliminary FLASH MEMORY A5h C0h Multi Plane Code Device Code 36h 76h 76h ...

Page 30

... K9F1208R0B K9F1208B0B K9F1208U0B Copy-Back Program Operation CLE ALE RE I/O 00h Column Page(Row) Address Address R/B On K9F1208X0B-Y,P or K9F1208X0B-V,F CE must be held low during 8Ah Column Page(Row) Address Address Busy ...

Page 31

... K9F1208R0B K9F1208B0B K9F1208U0B Device Operation PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command regis- ter along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation. ...

Page 32

... K9F1208R0B K9F1208B0B K9F1208U0B Figure 7. Read1 Operation CLE CE WE ALE R/B RE 00h Start Add.(4Cycle) I & NOTE: 1) After data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. On K9F1208U0B-Y,P or K9F1208U0B-V,F CE must be held low during tR ...

Page 33

... K9F1208R0B K9F1208B0B K9F1208U0B Figure 8. Read2 Operation CLE CE WE ALE R/B RE 50h Start Add.(4Cycle) I & Figure 9. Sequential Row Read1 Operation R/B I/O X 00h Start Add.(4Cycle) 01h & 00h Command) 1st half array Block Data Field The Sequential Read 1 and 2 operation is allowed only within a block and after the last page of a block is read- out, the sequential read operation must be terminated by bringing CE high ...

Page 34

... K9F1208R0B K9F1208B0B K9F1208U0B Figure 10. Sequential Row Read2 Operation R/B I/O Start Add.(4Cycle) X 50h & Don’t Care) PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528 bytes single page program cycle ...

Page 35

... K9F1208R0B K9F1208B0B K9F1208U0B BLOCK ERASE The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command(60h). Only address block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...

Page 36

... K9F1208R0B K9F1208B0B K9F1208U0B Restriction in addressing with Multi Plane Page Program While any block in each plane may be addressable for Multi-Plane Page Program, the five least significant addresses(A9-A13) for the selected pages at one operation must be the same. Figure 14 shows an example where 2nd page of each addressed block is selected for four planes. However, any arbitrary sequence is allowed in addressing multiple planes as shown in Figure15. Figure 14. Multi-Plane Program & ...

Page 37

... K9F1208R0B K9F1208B0B K9F1208U0B Copy-Back Program The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block ...

Page 38

... K9F1208R0B K9F1208B0B K9F1208U0B Multi-Plane Copy-Back Program Multi-Plane Copy-Back Program is an extension of one page Copy-Back Program into four plane operation. Since the device is equipped with four memory planes, activating the four sets of 528 bytes page registers enables a simultaneous Multi-Plane Copy- Back programming of four pages. Partial activation of four planes is also permitted. ...

Page 39

... K9F1208R0B K9F1208B0B K9F1208U0B ≈ ≈ ≈ ≈ ≈ ≈ FLASH MEMORY 39 Preliminary ...

Page 40

... K9F1208R0B K9F1208B0B K9F1208U0B READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired ...

Page 41

... The command register remains in Read ID mode until further commands are issued to it. Figure 21 shows the operation sequence. Figure 21. Read ID Operation 1 CLE CE WE ALE RE I 90h 00h Address. 1cycle t CEA WHR t REA Device ECh Code Maker code Device code Device Device Code K9F1208R0B K9F1208B0B K9F1208U0B 41 Preliminary FLASH MEMORY A5h C0h Multi-Plane code 36h 76h 76h ...

Page 42

... K9F1208R0B K9F1208B0B K9F1208U0B RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased ...

Page 43

... K9F1208R0B K9F1208B0B K9F1208U0B READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read . The R/B pin is normally high but transitions to low after program or erase command is written to the command register or ran- dom read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open- drain driver thereby allowing two or more R/B outputs to be Or-tied ...

Page 44

... K9F1208R0B K9F1208B0B K9F1208U0B 300n 200n 100n 300n 200n 100n 300n 200n 100n Rp value guidance V CC Rp(min, 1.8V part Rp(min, 2.7V part Rp(min, 3.3V part) = where I is the sum of the input currents of all devices tied to the R/B pin. L Rp(max) is determined by maximum permissible limit of tr ° ...

Page 45

... K9F1208R0B K9F1208B0B K9F1208U0B Data Protection & Power-up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.7V device), 2V(3.3V device). WP pin provides hard- ware protection and is recommended to be kept at V required before internal circuit gets ready for any command sequences as shown in Figure 24 ...

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