HYS64D16301GU INFINEON [Infineon Technologies AG], HYS64D16301GU Datasheet
HYS64D16301GU
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HYS64D16301GU Summary of contents
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Edition 2003-07 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 München, Germany Infineon Technologies AG 2003. © All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of ...
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... HYS[64/72]D64x20GU-x-B, HYS[64/72]D32x00[G/E]U-x-B, HYS64D16301GU-x-B Revision History: V1.1 Previous Version: V1.01 Page Subjects (major changes since last revision) all new data sheet template all replace bank by rank if DIMM related (4 bank SDRAM rank DIMM) 10 Table 6: Address Table updated 19ff Table 10ff: IDD conditions now in seperate table ...
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... Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 Current Conditions and Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules 5 V1.1, 2003-07 ...
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... CK2 1.2 Description The HYS[64/72]D64x20GU-x-B, HYS[64/72]D32x00[G/E]U-x-B, and HYS64D16301GU-x-B are industry standard 184-Pin Unbuffered Dual-In-Line Memory Modules (UDIMM) organized as 32M and 32M 72 and 64M 72 for ECC main memory applications. The memory array is designed with 256Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the printed circuit board ...
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... PC2700U-25330-B0 PC2100 (CL=2) HYS64D16301GU-7-B PC2100U-20330-C2 HYS64D32000GU-7-B PC2100U-20330-A1 HYS72D32000GU-7F-B PC2100U-20220-A1 HYS72D32000GU-7-B PC2100U-20330-A1 HYS64D64020GU-7-B PC2100U-20330-B1 HYS72D64020GU-7F-B PC2100U-20220-B1 HYS72D64020GU-7-B PC2100U-20330-B1 PC1600 (CL=2) HYS64D16301GU-8-B PC1600U-20330-C2 HYS64D32000GU-8-B PC1600U-20220-A1 HYS72D32000GU-8-B PC1600U-20220-A1 HYS64D64020GU-8-B PC1600U-20220-B1 HYS72D64020GU-8-B PC1600U-20220-B1 Table 3 Lead- and Halogene-Free DIMM Type Compliance Code PC2100 (CL=2) HYS64D32300EU-7-B PC2100U-20330-A1 Note: All part numbers end with a place code designating the silicon-die revision. Reference information available on request. Example: HYS72D32000GU-6-B, indicating rev. B dies are used for SDRAM components. The Compliance Code is printed on the module labels describing the speed sort (for example “ ...
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... SDA I/O SA0 - SA2 Input; O: Output; I/O: bidirectional In-/Output; AI: Analog Input; PWR: Power Supply; GND: Signal Ground; NC: Not Connected Note: S1 and CKE1 are used on two rank modules only Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B 1) Function Address Inputs Bank Selects Data Input/Output Check Bits ( 72 organization only) ...
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... DQ24 DQ25 80 36 DQS3 DQ26 84 Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules Backside Symbol PIN# Symbol CB2 94 DQ4 V 95 DQ5 CB3 96 V DDQD BA1 97 DM0/DQS9 Key 98 DQ6 99 DQ7 ...
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... Ranks 128MB 16M 64 1 256MB 32M 64 1 256MB 32M 72 1 512MB 64M 64 2 512MB 64M 72 2 Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules Backside Symbol PIN# Symbol V 132 DQS7 133 DQ31 DQ58 134 NC / CB4 DQ59 135 NC / CB5 V 136 V SS ...
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... SA0 SA1 SA2 Notes: 1. DQ-to-I/O wiring is shown as recommended but may 2. DQ/DQS/DM/CKE/S relationships must be main- 3. DQ, DQS, DM/DQS resistors: 22 ohms ± 5 BAx, Ax, RAS, CAS, WE resistors: 7.5 ohms ± DDR SDRAM DIMM HYS64D16301GU using 16 11 Pin Configuration S LDQS LDM DQ40 I/O 0 DQ41 ...
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... Wire per Clock Loading Table/Wiring Diagrams V SPD SPD DDQ REF Strap: see Note 4 DDID 64 DDR-I SDRAM DIMM HYS64D32x00GU / HYS64D32300EU 12 Unbuffered DDR SDRAM Modules Pin Configuration DM S DQS DQ32 I/O 0 DQ33 I DQ34 I/O 2 DQ35 I/O 3 I/O 4 DQ36 DQ37 I/O 5 DQ38 I/O 6 DQ39 I/O 7 ...
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... SA0 SA1 SA2 * Clock Wiring Clock SDRAMs Input 4 SDRAMs *CK0/CK0 *CK1/CK1 6 SDRAMs *CK2/CK2 6 SDRAMs * Wire per Clock Loading Table/Wiring Diagrams 64 DDR-I SDRAM DIMM HYS64D64x20GU using 8 13 Unbuffered DDR SDRAM Modules Pin Configuration DM S DQS DM I/O 0 DQ32 I/O 0 I/O 1 DQ33 I I/O 2 DQ34 I/O 2 I/O 3 DQ35 ...
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... DQS SCL SA0 SA1 V SPD DDQ V REF Strap: see Note 4 DDID 72 DDR-I SDRAM DIMM HYS72D32x00GU using 8 14 Unbuffered DDR SDRAM Modules Pin Configuration DM DQS S DQ32 I/O 0 DQ33 I DQ34 I/O 2 DQ35 I/O 3 I/O 4 DQ36 DQ37 I/O 5 DQ38 I/O 6 DQ39 I DQS ...
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... V D17 SS I I/O 3 DDID I/O 4 I/O 5 Strap: see Note 4 I/O 6 I/O 7 Serial PD SCL SA0 SA1 SA2 72 DDR-I SDRAM DIMM HYS72D64x20GU using 8 15 Unbuffered DDR SDRAM Modules Pin Configuration DQS I/O 0 DQ32 I/O 0 I/O 1 DQ33 I DQ34 I/O 2 I/O 2 I/O 3 DQ35 I/O 3 I/O 4 DQ36 I/O 4 I/O 5 DQ37 ...
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... DIMM Connector 1 DRAM Loads R = 120 ± 5% DIMM Connector Cap. = 1/2 DDR SDRAM input capacitance; 1.0 pF ± 20% Figure 6 Clock Net Wiring Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules DRAM1 DRAM2 DRAM3 4 DRAM Loads DRAM4 DRAM5 R = 120 ± 5% DRAM6 DIMM Connector DRAM1 Cap. ...
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... V DDQ DDQ – 0.04 REF REF 2.3 2 may not exceed ± REF (DC) REF V of the receiving device. REF 17 Unbuffered DDR SDRAM Modules Electrical Characteristics Values Unit Note/ Test typ. max. – DDQ 0.5 – +3.6 V – +3.6 V – +3.6 V – +70 C – ...
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... SS of the driving device and the V DDQ V (input overdrive the IH (max 0.3 V. Values are shown per DDR SDRAM component DDQ 18 Unbuffered DDR SDRAM Modules Electrical Characteristics Unit Note/ Test Condition – the receiving device is what determines noise ...
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... IH,MIN IL,MAX for DQ, DQS and DM. ILMAX IN REF IH,MIN RC RAS,MAX OUT 19 Unbuffered DDR SDRAM Modules Electrical Characteristics V = for DQ, DQS and DM. IN REF V = for DQ, DQS and DM. REF Symbol I DD0 I DD1 I DD2P I DD2F I DD2Q I DD3P I DD3N I DD4R I DD4W ...
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... ° data sheet values as: DDx [component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules I values will be measured differently depending on load DD I data sheet values as DDx 20 Unbuffered DDR SDRAM Modules Electrical Characteristics Unit Note ...
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... ° data sheet values as: DDx [component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules I values will be measured differently depending on load DD I data sheet values as DDx 21 Unbuffered DDR SDRAM Modules Electrical Characteristics 512MB ...
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... ° data sheet values as: DDx [component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules I values will be measured differently depending on load DD I data sheet values as DDx 22 Unbuffered DDR SDRAM Modules Electrical Characteristics Unit Note 512MB 72 2 ranks max ...
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... ° data sheet values as: DDx [component] with m and n number of components of rank 1 and 2; n=0 for 1 rank modules I values will be measured differently depending on load DD I data sheet values as DDx 23 Unbuffered DDR SDRAM Modules Electrical Characteristics Unit Note 512MB 72 2 ranks max ...
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... CK (write cycle) t Mode register set command MRD cycle time t Write preamble setup time WPRES Write postamble t WPST t Write preamble WPRE Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules –8 –7 DDR200 DDR266A Min. Max. Min. Max. –0.8 +0.8 –0.75 +0.75 –0.75 –0.8 +0.8 –0.75 +0.75 – ...
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... Inputs are not recognized as valid until 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note These parameters guarantee device timing, but they are not necessarily tested on each device. Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules –8 –7 DDR200 DDR266A Min ...
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... LZ t 0.75 1.25 DQSS t — +0.40 DQSQ — +0.45 t — +0.50 QHS — +0. – — QHS t 0.35 — DQSL,H 26 Unbuffered DDR SDRAM Modules Electrical Characteristics t . DQSS t is equal to the actual system clock CK –5 Unit Note/ Test Condition DDR400B Min. Max. 2)3)4)5) –0.6 +0.6 ns 2)3)4)5) –0.5 +0.5 ns 2)3)4)5) t 0.45 0.55 CK 2)3)4)5) 0.45 0. ...
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... Inputs are not recognized as valid until 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note These parameters guarantee device timing, but they are not necessarily tested on each device. Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B Unbuffered DDR SDRAM Modules Symbol –6 DDR333 Min. ...
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... For each of the terms, if not already an integer, round to the next highest integer. cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B . OL(ac) 28 Unbuffered DDR SDRAM Modules Electrical Characteristics t . DQSS t is equal to the actual system clock CK ...
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... SSTL_2 0 non-ECC/ECC 00 Self-Refresh 7 CLK 01 CCD 2, 4 & Unbuffered DDR SDRAM Modules SPD Contents 256MB 256MB 512MB rank 1 rank 2 ranks HEX HEX HEX ...
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... 0 not supported 00 not supported 256 MByte Unbuffered DDR SDRAM Modules SPD Contents 256MB 256MB 512MB rank 1 rank 2 ranks HEX HEX HEX ...
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... Manufacturer 72 Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number – 127 – 128 to 255 open for Customer use Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B 128MB 64 1 rank HEX 60 60 – ...
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... Table 18 SPD Codes for PC2100 Modules “–7” Byte Description 0 Number of SPD Bytes 128 1 Total Bytes in Serial PD 2 Memory Type 3 Number of Row Addresses 4 Number of Column Addresses 5 Number of DIMM Banks 6 Module Data Width 7 Module Data Width (cont’d) 8 Module Interface Levels ...
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... Table 18 SPD Codes for PC2100 Modules “–7” (cont’d) Byte Description 18 Supported CAS Latencies 19 CS Latencies 20 WE Latencies 21 SDRAM DIMM Module Attributes 22 SDRAM Device Attributes: General 23 Min. Clock Cycle Time at CAS Latency = 2 24 Access Time from Clock for Minimum Clock Cycle Time for ...
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... Table 18 SPD Codes for PC2100 Modules “–7” (cont’d) Byte Description Superset Information 41 Minimum Core Cycle t Time RC 42 Min. Auto Refresh t Cmd Cycle Time FRC 43 Maximum Clock Cycle Time Max. DQS-DQ Skew t DQSQ 45 X-Factor tQHS Superset Information ...
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... Table 19 SPD Codes for PC2100 Modules “–7F” Byte Description 0 Number of SPD Bytes 1 Total Bytes in Serial PD 2 Memory Type 3 Number of Row Addresses 4 Number of Column Addresses 5 Number of DIMM Banks 6 Module Data Width 7 Module Data Width (cont’d) 8 Module Interface Levels 9 SDRAM Cycle Time ...
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... Table 19 SPD Codes for PC2100 Modules “–7F” (cont’d) Byte Description 23 Min. Clock Cycle Time at CAS Latency = 2 24 Access Time from Clock for Minimum Clock Cycle Time for CL = 1.5 26 Access Time from Clock 1.5 27 Minimum Row Precharge Time 28 Minimum Row Act ...
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... Table 19 SPD Codes for PC2100 Modules “–7F” (cont’d) Byte Description Superset Information 62 SPD Revision 63 Checksum for Bytes Manufactures JEDEC Codes Manufacturer 72 Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date ...
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... Table 20 SPD Codes for PC2700 Modules “–6” Byte Description 0 Number of SPD Bytes 128 1 Total Bytes in Serial PD 2 Memory Type 3 Number of Row Addresses 4 Number of Column Addresses 5 Number of DIMM Banks 6 Module Data Width 7 Module Data Width (cont’d) 8 Module Interface Levels ...
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... Table 20 SPD Codes for PC2700 Modules “–6” (cont’d) Byte Description 18 Supported CAS Latencies 19 CS Latencies 20 WE Latencies 21 SDRAM DIMM Module Attributes 22 SDRAM Device Attributes: General 23 Min. Clock Cycle Time at CAS Latency = 2 24 Access Time from Clock for Minimum Clock Cycle Time for ...
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... Table 20 SPD Codes for PC2700 Modules “–6” (cont’d) Byte Description Superset Information 41 Minimum Core Cycle t Time RC 42 Min. Auto Refresh t Cmd Cycle Time FRC 43 Maximum Clock Cycle Time Max. DQS-DQ Skew t DQSQ 45 X-Factor tQHS Superset Information ...
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... Table 21 SPD Codes for PC3200 Modules “–5” Byte Description 0 Programmed SPD Bytes in E2PROM 1 Total number of Bytes in E2PROM 2 Memory Type DDR-I = 07h Row Addresses 4 # Number of Column Addresses DIMM Banks 6 Data Width (LSB) 7 Data Width (MSB) 8 Interface Voltage Levels ...
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... Table 21 SPD Codes for PC3200 Modules “–5” (cont’d) Byte Description 29 tRCDmin [ns] 30 tRASmin [ns] 31 Module Density per Bank 32 tAS, tCS [ns] 33 tAH, TCH [ns] 34 tDS [ns] 35 tDH [ns not used 40 41 tRCmin [ns] 42 tRFCmin [ns] 43 tCKmax [ns] 44 tDQSQmax [ns] ...
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... Table 21 SPD Codes for PC3200 Modules “–5” (cont’d) Byte Description 76 Module Part Number, Char 4 77 Module Part Number, Char 5 78 Module Part Number, Char 6 79 Module Part Number, Char 7 80 Module Part Number, Char 8 81 Module Part Number, Char 9 ...
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... Package Outlines 1 2.36 ±0.1 ø0 64. MIN. Detail of contacts 1.27 1 ±0. ECC modules only Burr max. 0.4 allowed Figure 7 Package Outline - Raw Card C (128 MByte, 1 Rank Module) Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B 133.35 128. 6.62 C 2.175 6. 1.27 = 120.65 1.8 ±0.1 0.1 0 Unbuffered DDR SDRAM Modules ...
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... A B 64. MIN. Detail of contacts 1.27 1 ±0. ECC modules only Burr max. 0.4 allowed Figure 8 Package Outline - Raw Card A (256 MByte, 1 Rank Module, –7 and –8) Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B 133.35 128. 6.62 C 2.175 6. 1.27 = 120.65 1.8 ±0 ...
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... A B 64. MIN. Detail of contacts 1.27 1 ±0. ECC modules only Burr max. 0.4 allowed Figure 9 Package Outline - Raw Card B (512 MByte, 2 Rank Module, –7 and –8) Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B 133.35 128. 6.62 C 2.175 6. 1.27 = 120.65 1.8 ±0 ...
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... A B 64. MIN. Detail of contacts 1.27 1 ±0. ECC modules only Burr max. 0.4 allowed Figure 10 Package Outline - Raw Card A (256 MByte, 1 Rank Module, –5 and –6, ECC) Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B 133.35 128. 6.62 C 2.175 6. 1.27 = 120.65 1.8 ±0.1 0 ...
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... A B 64. MIN. Detail of contacts 1.27 1 ±0. ECC modules only Burr max. 0.4 allowed Figure 11 Package Outline - Raw Card B (512 MByte, 2 Rank Module, –5 and –6, ECC) Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B 133.35 128. 6.62 C 2.175 6. 1.27 = 120.65 1.8 ±0.1 0 ...
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... A B 64. MIN. Detail of contacts 1.27 1 ±0.05 Burr max. 0.4 allowed Figure 12 Package Outline - Raw Card A (256 MByte, 1 Rank Module, –5 and –6, Non ECC) Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B 133.35 128.95 A 6.62 C 2.175 6. 1.27 = 120.65 1.8 ±0.1 0.1 0 Unbuffered DDR SDRAM Modules ...
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... A B 64. MIN. Detail of contacts 1.27 1 ±0.05 Burr max. 0.4 allowed Figure 13 Package Outline - Raw Card B (512 MByte, 2 Rank Module, –5 and –6, Non ECC) Data Sheet HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B 133.35 128.95 A 6.62 C 2.175 6. 1.27 = 120.65 1.8 ±0.1 0 Unbuffered DDR SDRAM Modules ...
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Published by Infineon Technologies AG ...