M391B5273DH0 SAMSUNG [Samsung semiconductor], M391B5273DH0 Datasheet - Page 20

• Manufacturer Part Number: M391B5273DH0
• Description: 240pin Unbuffered DIMM based on 2Gb D-die
• Manufacturer: SAMSUNG [Samsung semiconductor]

Unbuffered DIMM
13. AC & DC Output Measurement Levels
13.1 Single Ended AC and DC Output Levels
[ Table 8 ] Single Ended AC and DC output levels
NOTE : 1. The swing of +/-0.1 x V
13.2 Differential AC and DC Output Levels
[ Table 9 ] Differential AC and DC output levels
NOTE : 1. The swing of +/-0.2xV
13.3 Single-ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V
for single ended signals as shown in below.
[ Table 10 ] Single ended Output slew rate definition
NOTE : Output slew rate is verified by design and characterization, and may not be subject to production test.
[ Table 11 ] Single ended output slew rate
Description : SR : Slew Rate
Q : Query Output (like in DQ, which stands for Data-in, Query-Output)
se : Single-ended Signals
For Ron = RZQ/7 setting
NOTE : 1) In two cased, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
Single ended output slew rate for rising edge
Single ended output slew rate for falling edge
Single ended output slew rate
V
V
V
V
V
Symbol
OM
OH
OL
OH
OL
V
V
Symbol
OHdiff
OLdiff
(DC)
(AC)
(DC)
(AC)
(DC)
- Case_2 is defined for a single DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the
- Case_1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low of low to high) while all remaining DQ
load of 25Ω to V
load of 25Ω to V
(AC)
Parameter
(AC)
Parameter
DC output high measurement level (for IV curve linearity)
DC output mid measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
AC output high measurement level (for output SR)
AC output low measurement level (for output SR)
signals in the same byte lane are static (i.e they stay at either high or low).
remaining DQ signal switching into the opposite direction, the regular maximum limit of 5 V/ns applies.
Parameter
AC differential output high measurement level (for output SR)
AC differential output low measurement level (for output SR)
Description
TT
TT
=V
=V
DDQ
DDQ
DDQ
DDQ
/2.
/2 at each of the differential outputs.
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40Ω and an effective test
Symbol
SRQse
Min
2.5
Figure 7. Single-ended Output Slew Rate Definition
DDR3-800
delta
Max
TFse
datasheet
5
V
V
OH
From
OL
(AC)
(AC)
Measured
Min
2.5
DDR3-1066
- 20 -
Max
V
V
5
OH
OL
To
(AC)
(AC)
delta
TRse
Min
2.5
DDR3-1333
DDR3-800/1066/1333/1600/1866
DDR3-800/1066/1333/1600/1866
Max
V
V
V
V
V
5
OH(AC)
TT
OL(AC)
TT
TT
0.8 x V
0.5 x V
0.2 x V
+ 0.1 x V
- 0.1 x V
+0.2 x V
-0.2 x V
Min
2.5
DDR3-1600
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
OH
OH
Defined by
Delta TRse
Delta TFse
(AC)-V
(AC)-V
Max
5
DDR3 SDRAM
OL
OL
(AC)
(AC)
Min
2.5
DDR3-1866
OL
Units
Units
(AC) and V
V
V
V
V
V
V
V
Max
5
1)
Rev. 1.4
NOTE
NOTE
OH
Units
V/ns
1
1
1
1
(AC)