M391B5273DH0 SAMSUNG [Samsung semiconductor], M391B5273DH0 Datasheet - Page 33

• Manufacturer Part Number: M391B5273DH0
• Description: 240pin Unbuffered DIMM based on 2Gb D-die
• Manufacturer: SAMSUNG [Samsung semiconductor]

Unbuffered DIMM
[ Table 20 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333 (Cont.)
Command and Address Timing
DLL locking time
internal READ Command to PRECHARGE Command delay
Delay from start of internal write transaction to internal read com-
mand
WRITE recovery time
Mode Register Set command cycle time
Mode Register Set command update delay
CAS to CAS command delay
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
ACTIVE to ACTIVE command period for 1KB page size
ACTIVE to ACTIVE command period for 2KB page size
Four activate window for 1KB page size
Four activate window for 2KB page size
Command and Address setup time to CK, CK referenced to
V
Command and Address hold time from CK, CK referenced to
V
Control & Address Input pulse width for each input
Calibration Timing
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation short calibration time
Reset Timing
Exit Reset from CKE HIGH to a valid command
Self Refresh Timing
Exit Self Refresh to commands not requiring a locked DLL
Exit Self Refresh to commands requiring a locked DLL
Minimum CKE low width for Self refresh entry to exit timing
Valid Clock Requirement after Self Refresh Entry (SRE) or Power-
Down Entry (PDE)
Valid Clock Requirement before Self Refresh Exit (SRX) or Power-
Down Exit (PDX) or Reset Exit
IH
IH
(AC) / V
(DC) / V
IL
IL
(AC) levels
(DC) levels
Parameter
Speed
tDAL(min)
tIH(base)
tIS(base)
tIS(base)
tCKESR
tCKSRE
tCKSRX
Symbol
tZQoper
tXSDLL
tMPRR
AC175
AC150
DC100
tZQinitI
tZQCS
tDLLK
tWTR
tMRD
tMOD
tCCD
tRRD
tRRD
tFAW
tFAW
tRTP
tRAS
tXPR
tIPW
tWR
tXS
datasheet
max(5nCK,tRF
(12nCK,15ns)
tRFC + 10ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,10ns)
(4nCK,10ns)
tCKE(min) +
max(5nCK,
tDLLK(min)
max(5nCK,
max(5nCK,
C + 10ns)
200+150
See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin” on page 42
10ns)
10ns)
1tCK
MIN
max
max
max
max
max
512
200
275
900
512
256
15
40
50
64
4
4
1
DDR3-800
- 33 -
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WR + roundup (tRP / tCK(AVG))
max(5nCK,tRF
(12nCK,15ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
tRFC + 10ns)
(4nCK,10ns)
tCKE(min) +
tDLLK(min)
max(5nCK,
max(5nCK,
max(5nCK,
C + 10ns)
125+150
10ns)
10ns)
1tCK
37.5
MIN
max
max
max
max
max
512
125
200
780
512
256
15
50
64
4
4
1
DDR3-1066
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max(5nCK,tRF
(12nCK,15ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
tRFC + 10ns)
tCKE(min) +
(4nCK,6ns)
max(5nCK,
tDLLK(min)
max(5nCK,
max(5nCK,
C + 10ns)
65+125
10ns)
10ns)
1tCK
MIN
max
max
max
max
max
512
140
620
512
256
15
30
45
65
64
4
4
1
DDR3-1333
DDR3 SDRAM
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Units
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
ns
ns
ns
ns
ps
ps
ps
ps
Rev. 1.4
b,16,27
NOTE
e,18
b,16
b,16
22
28
23
e
e
e
e
e
e
e