M391B5273DH0 SAMSUNG [Samsung semiconductor], M391B5273DH0 Datasheet - Page 37

• Manufacturer Part Number: M391B5273DH0
• Description: 240pin Unbuffered DIMM based on 2Gb D-die
• Manufacturer: SAMSUNG [Samsung semiconductor]

Unbuffered DIMM
[ Table 21 ] Timing Parameters by Speed Bins for DDR3-1600, DDR3-1866
Power Down Timing
Exit Power Down with DLL on to any valid command;Exit Pre-
charge Power Down with DLL
frozen to commands not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to commands re-
quiring a locked DLL
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Timing of WR command to Power Down entry
(BC4MRS)
Timing of WRA command to Power Down entry
(BC4MRS)
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT high time without write command or with write command
and BC4
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power-Down with DLL fro-
zen)
Asynchronous RTT turn-off delay (Power-Down with DLL fro-
zen)
RTT turn-on
RTT_NOM and RTT_WR turn-off time from ODTLoff reference
RTT dynamic change skew
First DQS/DQS rising edge after write leveling mode is pro-
grammed
DQS/DQS delay after write leveling mode is programmed
Write leveling setup time from rising CK, CK crossing to rising
DQS, DQS crossing
Write leveling hold time from rising DQS, DQS crossing to rising
CK, CK crossing
Write leveling output delay
Write leveling output error
ODT Timing
Write Leveling Timing
Parameter
Speed
tWRAPDEN
tWRAPDEN
tMRSPDEN
tWLDQSEN
tACTPDEN
tREFPDEN
tWRPDEN
tWRPDEN
tPRPDEN
tRDPDEN
tWLMRD
tCPDED
tAONPD
Symbol
tAOFPD
tXPDLL
ODTH4
ODTH8
tWLOE
tWLO
tCKE
tAON
tAOF
tADC
tWLS
tWLH
tXP
tPD
datasheet
WL + 4 +WR +1
WL +2 +WR +1
WL + 4 +(tWR/
WL + 2 +(tWR/
(3nCK,6ns)
(3nCK,5ns)
tMOD(min)
tCKE(min)
RL + 4 +1
tCK(avg))
tCK(avg))
(10nCK,
24ns)
-225
MIN
max
max
max
165
165
0.3
0.3
40
25
1
1
1
1
4
6
2
2
0
0
DDR3-1600
- 37 -
9*tREFI
MAX
225
8.5
8.5
0.7
0.7
7.5
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max(10nCK,24ns)
WL + 4 +WR +1
max(3nCK,6ns)
max(3nCK,5ns)
WL +2 +WR +1
WL + 4 +(tWR/
WL + 2 +(tWR/
tMOD(min)
tCKE(min)
RL + 4 +1
tCK(avg))
tCK(avg))
MIN
-195
140
140
0.3
0.3
40
25
2
1
1
1
4
6
2
2
0
0
DDR3-1866
9*tREFI
DDR3 SDRAM
MAX
195
8.5
8.5
0.7
0.7
7.5
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
Units
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
tCK
tCK
tCK
ns
ns
ps
ps
ps
ns
ns
Rev. 1.4
NOTE
20,21
15
20
20
10
10
7,f
8,f
2
9
9
3
3
f