M378B2873GB0 SAMSUNG [Samsung semiconductor], M378B2873GB0 Datasheet - Page 34

• Manufacturer Part Number: M378B2873GB0
• Description: 240pin Unbuffered DIMM based on 1Gb G-die
• Manufacturer: SAMSUNG [Samsung semiconductor]

Unbuffered DIMM
[ Table 20 ] Timing Parameters by Speed Bins for DDR3-800 to DDR3-1333
Power Down Timing
Exit Power Down with DLL on to any valid command;Exit Pre-
charge Power Down with DLL
frozen to commands not requiring a locked DLL
Exit Precharge Power Down with DLL frozen to commands re-
quiring a locked DLL
CKE minimum pulse width
Command pass disable delay
Power Down Entry to Exit Timing
Timing of ACT command to Power Down entry
Timing of PRE command to Power Down entry
Timing of RD/RDA command to Power Down entry
Timing of WR command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Timing of WRA command to Power Down entry
(BL8OTF, BL8MRS, BC4OTF)
Timing of WR command to Power Down entry
(BC4MRS)
Timing of WRA command to Power Down entry
(BC4MRS)
Timing of REF command to Power Down entry
Timing of MRS command to Power Down entry
ODT high time without write command or with write command
and BC4
ODT high time with Write command and BL8
Asynchronous RTT turn-on delay (Power-Down with DLL fro-
zen)
Asynchronous RTT turn-off delay (Power-Down with DLL fro-
zen)
RTT turn-on
RTT_NOM and RTT_WR turn-off time from ODTLoff reference
RTT dynamic change skew
First DQS/DQS rising edge after write leveling mode is pro-
grammed
DQS/DQS delay after write leveling mode is programmed
Write leveling setup time from rising CK, CK crossing to rising
DQS, DQS crossing
Write leveling hold time from rising DQS, DQS crossing to rising
CK, CK crossing
Write leveling output delay
Write leveling output error
ODT Timing
Write Leveling Timing
Parameter
Speed
tWRAPDEN
tWRAPDEN
tWLDQSEN
tMRSPDEN
tACTPDEN
tREFPDEN
tWRPDEN
tWRPDEN
tRDPDEN
tPRPDEN
tWLMRD
tAONPD
tCPDED
tAOFPD
Symbol
tXPDLL
ODTH4
ODTH8
tWLOE
tAON
tADC
tWLS
tWLH
tWLO
tCKE
tAOF
tXP
tPD
datasheet
WL+4+WR +1
WL +2 +WR
tMOD(min)
tCKE(min)
RL + 4 +1
tCK(avg))
tCK(avg))
(10nCK,
(3nCK,
(3nCK,
WL + 4
+(tWR/
WL + 2
+(tWR/
7.5ns)
7.5ns)
24ns)
max
max
max
-400
MIN
325
325
0.3
0.3
+1
40
25
1
1
1
1
4
6
2
2
0
0
DDR3-800
- 34 -
9*tREFI
MAX
400
8.5
8.5
0.7
0.7
9
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WL+4+WR+1
WL +2 +WR
tMOD(min)
tCKE(min)
RL + 4 +1
tCK(avg))
tCK(avg))
5.625ns)
(10nCK,
(3nCK,
(3nCK,
WL + 4
+(tWR/
WL + 2
+(tWR/
7.5ns)
24ns)
-300
MIN
max
max
max
245
245
0.3
0.3
+1
40
25
1
1
1
1
4
6
2
2
0
0
DDR3-1066
9*tREFI
MAX
300
8.5
8.5
0.7
0.7
9
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
WL+4+WR+1
WL +2 +WR
(3nCK,6ns)
tMOD(min)
tCKE(min)
RL + 4 +1
tCK(avg))
tCK(avg))
5.625ns)
(10nCK,
WL + 4
WL + 2
(3nCK,
+(tWR/
+(tWR/
24ns)
-250
MIN
max
max
max
195
195
0.3
0.3
+1
40
25
1
1
1
1
4
6
2
2
0
0
DDR3-1333
DDR3 SDRAM
9*tREFI
MAX
250
8.5
8.5
0.7
0.7
9
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
Units
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
nCK
tCK
tCK
tCK
ns
ns
ps
ps
ps
ns
ns
Rev. 1.2
NOTE
20,21
15
20
20
10
10
7,f
8,f
2
9
9
3
3
f