HYS64T128920HU QIMONDA [Qimonda AG], HYS64T128920HU Datasheet - Page 23

• Manufacturer Part Number: HYS64T128920HU
• Description: 240-Pin Unbuffered DDR2 SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
28) For these parameters, the DDR2 SDRAM device is characterized and verified to support
29) DAL = WR + RU{
30)
31)
32)
33) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
34) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
35) When the device is operated with input clock jitter, this parameter needs to be derated by {–
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
of the division is not already an integer, round up to the next highest integer.
DDR2–533 at
t
t
t
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of
the ODT resistance is fully on. Both are measured from
Both are measured from
–
into a DDR2–667 SDRAM has
then
+ {–
nRP
DAL.nCK
WTR
CKE.MIN
t
t
t
JIT.PER.MAX
JIT.DUTY.MAX
ERR(6-10PER).MIN
t
t
= RU{
t
is at lease two clocks (2 x
JIT.PER.MAX
JIT.DUTY.MAX
t
JIT.DUTY.MIN
AOF.MIN(DERATED)
of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
= WR [nCK] +
t
RP
= 1.1 x
/
= 0.6 x
t
= + 93 ps, then
t
CK
CK.AVG
= + 93 ps, then
–
t
} of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter
RP
= 3.75 ns with
t
t
ERR(6-10PER).MIN
IS
(ns) /
t
CK.AVG
+ 2 x
=
t
} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
CK.AVG
t
t
nRP.nCK
AOF.MIN
t
t
AOFD
CK
t
CK
+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
tRPST
+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For
+
.
tHZ,tRPST
t
= WR + RU{
+ {–
RPRE.MIN(DERATED)
t
t
tHZ
t
RPST.MIN(DERATED)
CK
ERR(6-10PER).MIN
t
} = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (Caution on the MIN/MAX usage!)
t
IH
end point
WR
) independent of operation frequency.
.
t
JIT.DUTY.MAX
programmed to 4 clocks.
T1 T2
end point
t
RP
[ps] /
= – 272 ps,
–
=
=
t
= 2*T1-T2
ERR(6-10PER).MAX
t
RPRE.MIN
t
RPST.MIN
t
CK.AVG
VOH - x mV
VOH - 2x mV
VOL + 2x mV
VOL + x mV
t
AOND
+
[ps] }, where WR is the value programmed in the EMR.
t
+
ERR(6- 10PER).MAX
t
JIT.PER.MIN
t
JIT.DUTY.MIN
.
t
DAL
} = – 450 ps + {– 94 ps – 293 ps} = – 837 ps and
23
= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
VTT + 2x mV
VTT + x mV
VTT - x mV
VTT - 2x mV
= 0.9 x
= 0.4 x
Method for calculating transitions and endpoint
= + 293 ps,
tLZ,tRPRE
t
t
CK.AVG
CK
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
t
CK.AVG
refers to the application clock period. Example: For
– 72 ps = + 2178 ps and
begin point
– 72 ps = + 928 ps and
t
JIT.DUTY.MIN
T1
t
t
nPARAM
JIT.DUTY.MAX
T2
Unbuffered DDR2 SDRAM Modules
= 2*T1-T2
tLZ
tRPRE
= RU{
= – 106 ps and
begin point
t
t
JIT.PER
JIT.DUTY
–
t
t
nRP
RP
t
t
PARAM
ERR(6-10PER).MAX
= 15 ns, the device will support
= RU{
of the input clock. (output
t
of the input clock. (output
t
RPRE.MAX(DERATED)
RPST.MAX(DERATED)
/
t
t
AOF.MAX(DERATED)
CK.AVG
t
Internet Data Sheet
RP
t
JIT.DUTY.MAX
/
t
t
JIT.DUTY.MIN
JIT.PER.MIN
t
CK.AVG
}, which is in clock
FIGURE 3
} and {–
t
RP
}, which is in
, if the result
= + 94 ps,
=
t
=
= – 72 ps
JIT.DUTY.MIN
=
= – 72 ps
t
t
RPRE.MAX
RPST.MAX
t
AOF.MAX