GS882Z18AB GSI [GSI Technology], GS882Z18AB Datasheet - Page 23

• Manufacturer Part Number: GS882Z18AB
• Description: 9Mb Pipelined and Flow Through Synchronous NBT SRAM
• Manufacturer: GSI [GSI Technology]

Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM.
It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the
controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.
ID Register Contents
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
Rev: 1.04 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Tap Controller Instruction Set
Bit #
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
Revision
Code
Die
TDI
TMS
TCK
·
·
·
·
Not Used
Test Access Port (TAP) Controller
Bypass Register
Instruction Register
ID Code Register
2
31 30 29
0
JTAG TAP Block Diagram
Boundary Scan Register
·
1
0
Control Signals
23/35
·
·
· · ·
·
2
1
0
GS882Z18/36AB/D-250/225/200/166/150/133
·
Configuration
·
I/O
·
·
GSI Technology
TDO
JEDEC Vendor
ID Code
© 2001, GSI Technology
0