PPC440EP-3PBFFFCX AMCC [Applied Micro Circuits Corporation], PPC440EP-3PBFFFCX Datasheet - Page 73

• Manufacturer Part Number: PPC440EP-3PBFFFCX
• Description: Power PC 440EP Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

DDR SDRAM Write Operation
The following diagram illustrates the relationship among the signals involved with a DDR write operation.
Figure 8. DDR SDRAM Write Cycle Timing
AMCC Proprietary
440EP – PPC440EP Embedded Processor
MemClkOut0(90)
MemClkOut0
T
T
T
T
T
T
HD
SA
SD
DS
SK
HA
Addr/Cmd
MemData
PLB Clk
= Setup time for address and command signals to MemClkOut0(90)
= Delay from rising/falling edge of clock to the rising/falling edge of DQS
= Delay from rising edge of MemClkOut0(0) to rising/falling edge of signal (skew)
= Hold time for address and command signals from MemClkOut0(90)
= Setup time for data signals (minimum time data is valid before rising/falling edge of DSQ)
= Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ)
DQS
T
SK
T
T
SA
HA
T
DS
T
SD
T
T
HD
DS
T
SD
T
HD
Revision 1.26 – April 25, 2007
Data Sheet
73