PPC440GR-3PBFFFCX AMCC [Applied Micro Circuits Corporation], PPC440GR-3PBFFFCX Datasheet - Page 53

• Manufacturer Part Number: PPC440GR-3PBFFFCX
• Description: Power PC 440GR Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

Table 7. Signal Functional Description (Sheet 4 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
AMCC Proprietary
440GR – PPC440GR Embedded Processor
External Slave Peripheral Interface
DMAAck0:3
DMAReq0:3
EOT0:3/TC0:3
PerAddr02:07
PerAddr08:31
PerBLast
PerCS0:5
PerData00:15
PerOE
PerReady
PerR/W
PerWBE0:1
PerErr
Signal Name
End Of Transfer/Terminal Count.
Used by the PPC440GR to indicate that data transfers have
occurred.
Used by slave peripherals to indicate they are prepared to
transfer data.
Peripheral address bus used by PPC440GR when not in
external master mode, otherwise used by external master.
Peripheral address bus used by PPC440GR when not in
external master mode, otherwise used by external master.
Used by either the peripheral controller, DMA controller, or
external master to indicates the last transfer of a memory
access.
External peripheral device select.
Peripheral data bus used by PPC440GR when not in external
master mode, otherwise used by external master.
Note: PerData00 is the most significant bit (msb) on this bus.
Used by either peripheral controller or DMA controller
depending upon the type of transfer involved. When the
PPC440GR is the bus master, it enables the selected device to
drive the bus.
Used by a peripheral slave to indicate it is ready to transfer
data.
Used by the PPC440GR when not in external master mode, as
output by either the peripheral controller or DMA controller
depending upon the type of transfer involved. High indicates a
read from memory, low indicates a write to memory.
Otherwise, it used by the external master as an input to
indicate the direction of transfer.
External peripheral data bus byte enables.
External Error. Used as an input to record external slave
peripheral errors.
Description
Preliminary Data Sheet
Revision 1.16 – July 19, 2006
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Multiplex
Multiplex
Multiplex
Type
Notes
1, 5
1, 5
1, 2
1, 4
1, 2
1, 2
1, 5
2
1
2
53