ppc440gr-3jb667cz Applied Micro Circuits Corporation (AMCC), ppc440gr-3jb667cz Datasheet
ppc440gr-3jb667cz
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ppc440gr-3jb667cz Summary of contents
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... Programmable General Purpose Timers (GPT). Description Designed specifically to address high-end embedded applications, the PowerPC 440GR (PPC440GR) provides a high-performance, low- power solution that interfaces to a wide range of peripherals and incorporates on-chip power management features. This chip contains a high-performance RISC ...
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... General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Universal Interrupt Controller (UIC JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Serial EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 2 440GR – PPC440GR Embedded Processor AMCC Proprietary ...
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... PPC440GR Embedded Processor Figures Figure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. PPC440GR Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. 35mm, 456-Ball E-PBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 4. Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 5. Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figure 6. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 7. Output Delay and Float Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 8. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figure 9 ...
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... Revision 1.19 – May 07, 2008 Preliminary Data Sheet Table 25. I/O Timing—DDR SDRAM T Table 26. I/O Timing—DDR SDRAM T Table 27. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 4 440GR – PPC440GR Embedded Processor and and SIN DIN AMCC Proprietary ...
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... Grade 3 Reliability Package Note: The example P/N above is lead-free, capable of running at 667 MHz, and is shipped in tape-and-reel packaging. AMCC Proprietary Revision Package Level 35mm, 456 ball, E-PBGA PPC440GR-3JB667CZ Revision 1.19 – May 07, 2008 Preliminary Data Sheet PVR Value JTAG ID B 0x422218D4 0x2A950049 Shipping Package ...
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... Performance Monitor PLB4 (128 bits) Controller DDR SDRAM Controller 266MHz data rate - 13-bit addr - 32-bit data The PPC440GR is a system on a chip (SOC) using IBM CoreConnect Bus 6 440GR – PPC440GR Embedded Processor Power Mgmt DCRs GPIO DCR Bus Trace On-chip Peripheral Bus (OPB) ...
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... PPC440GR Embedded Processor Address Maps The PPC440GR incorporates two address maps. The first is a fixed processor System Memory Address Map. This address map defines the possible contents of various address regions which the processor can access. The second is the DCR Address Map for Device Configuration Registers (DCRs). The DCRs are accessed by software running on the PPC440GR processor through the use of Table 1 ...
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... Boot space (EBC Bank 0 and PCI) Notes: 1. DDR SDRAM can be located anywhere in the Local Memory area of the memory map. 2. EBC and PCI are relocatable, but this map reflects the suggested configuration. 8 440GR – PPC440GR Embedded Processor Sub Function Start Address 0 EF50 0000 0 EF60 0000 ...
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... PPC440GR Embedded Processor Table 2. DCR Address Map (4KB of Device Configuration Registers) Function 1 Total DCR Address Space By function: Reserved Clocking Power On Reset System DCRs Memory Controller External Bus Controller Reserved PLB 128 Performance Monitor Reserved PLB 128 to PLB 64 Bridge Out ...
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... Data value compare – Single step, branch, and trap events – Non-invasive real-time trace interface • 24 DSP instructions – Single cycle multiply and multiply-accumulate – integer multiply – -> 32-bit MAC 10 440GR – PPC440GR Embedded Processor AMCC Proprietary ...
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... PPC440GR Embedded Processor Internal Buses The PowerPC 440GR features four standard on-chip buses: two Processor Local Buses (PLBs), one On-Chip Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI bridge connect to the PLBs ...
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... CAS latencies of 2, 2.5 and 3 supported • DDR200/266 support • Page mode accesses (up to eight open pages) with configurable paging policy • Programmable address mapping and timing • Hardware and software initiated self-refresh • Power management (self-refresh, suspend, sleep) 12 440GR – PPC440GR Embedded Processor AMCC Proprietary ...
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... External master can control EBC slaves for own access and control Ethernet Controller Interface Ethernet support provided by the PPC440GR interfaces to the physical layer but the PHY is not included on the chip: • One to two 10/100 interfaces running in full- and half-duplex modes – ...
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... One programmable interrupt request signal • Provides full management of all IIC bus protocols • Programmable error recovery • Includes an integrated boot-strap controller (BSC) that is multiplexed with the IIC0 interface 14 440GR – PPC440GR Embedded Processor 2 C Specification, dated 1995 AMCC Proprietary ...
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... PPC440GR Embedded Processor Serial Peripheral Interface (SPI/SCP) The Serial Peripheral Interface (also known as the Serial Communications Port full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB. ...
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... Programmable interrupt priority ordering • Programmable critical interrupt vector for faster vector processing JTAG Features include: • IEEE 1149.1 Test Access Port • IBM RISCWatch Debugger support • JTAG Boundary Scan Description Language (BSDL) 16 440GR – PPC440GR Embedded Processor AMCC Proprietary ...
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... PPC440GR Embedded Processor Package Diagram Figure 3. 35mm, 456-Ball E-PBGA Package Top View Lot Number Part Number Gold Gate Release Corresponds to A1 Ball Location Notes: 0.20 Bottom View ± 35.0 0 ...
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... Time within 5°C of Actual Peak Temperature Ramp-down Rate Time 25°C to Peak Temperature Table 4. JEDEC Moisture Sensitivity Level and Ball Composition MSL Level Solder Ball Metallurgy 18 440GR – PPC440GR Embedded Processor Sn-Pb Eutectic Assembly 3°C/second max 100°C 150°C 60-120 Seconds 183°C 60-150 Seconds 225 +0/-5° ...
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... PPC440GR Embedded Processor Signal Lists The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the signal appears. Multiplexed signals are shown with the default signal (following reset) not in brackets and alternate signals in brackets. Multiplexed signals appear alphabetically multiple times in the list— ...
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... EMC0TxD1, EMC1TxD]GPIO17 [EMCTxD2, EMC1TxD0]GPIO18[NFCLE] [EMCTxD3, EMC1TxD1]GPIO19[NFALE] [EMCTxEn, EMC0TxEn, EMCSync]GPIO24 [EMCTxErr, EMC1TxEn]GPIO23[NFWEn] [EOT0/TC0][IRQ9]GPIO48 [EOT1/TC1][IRQ6]GPIO45 [EOT2/TC2][PerAddr05]GPIO02 [EOT3/TC3][PerAddr02]GPIO05 [ExtAck]GPIO30 [ExtReq]GPIO27 ExtReset 20 440GR – PPC440GR Embedded Processor Ball Interface Group P02 N02 M01 M02 DDR SDRAM N03 N04 L02 M03 AC16 ...
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... PPC440GR Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 3 of 24) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 22 440GR – PPC440GR Embedded Processor Ball Interface Group M15 M25 N05 N11 N13 N14 N15 N16 P11 P12 P13 P14 P16 P22 R12 R14 ...
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... PPC440GR Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 5 of 24) Signal Name GND GND GND GND GND GND GND GND GND GND GND GND AMCC Proprietary Revision 1.19 – May 07, 2008 Preliminary Data Sheet Ball Interface Group AD03 AD24 AE01 AE02 ...
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... GPIO20[EMCRxErr, EMC0RxErr] GPIO21[EMCDV, EMC1CrsDV][NFREn] GPIO22[EMCCrS, EMC0CrsDV] GPIO23[EMCTxErr, EMC1TxEn][NFWEn] GPIO24[EMCTxEn, EMC0TxEn, EMCSync] GPIO25[EMCCD, EMC1RxErr][NFRdyBusy] GPIO26 GPIO27[ExtReq] GPIO28 GPIO29[HoldAck] GPIO30[ExtAck] GPIO31[BusReq] 24 440GR – PPC440GR Embedded Processor Ball Interface Group C08 B06 A05 D08 C07 B04 C06 A04 B07 B10 A10 ...
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... PPC440GR Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 7 of 24) Signal Name GPIO32 GPIO33 GPIO34[UART0_DCD/UART1_CTS/UART2_Tx] GPIO35[UART0_DSR/UART1_RTS/UART2_Rx] GPIO36[UART0_CTS/UART3_Rx] GPIO37[UART0_RTS/UART3_Tx] GPIO38[UART0_DTR/UART1_Tx] GPIO39[UART0_RI/UART1_Rx] GPIO40[IRQ0] GPIO41[IRQ1] GPIO42[IRQ2] GPIO43[IRQ3] GPIO44[IRQ4][DMAAck1] GPIO45[IRQ6][EOT1/TC1] GPIO46[IRQ7][DMAReq0] GPIO47[IRQ8][DMAAck0] GPIO48[IRQ9][EOT0/TC0] GPIO49[TrcBS0] GPIO50[TrcBS1] GPIO51[TrcBS2] GPIO52[TrcES0] GPIO53[TrcES1] GPIO54[TrcES2] ...
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... MemAddr00 MemAddr01 MemAddr02 MemAddr03 MemAddr04 MemAddr05 MemAddr06 MemAddr07 MemAddr08 MemAddr09 MemAddr10 MemAddr11 MemAddr12 MemClkOut0 MemClkOut0 26 440GR – PPC440GR Embedded Processor Ball Interface Group U24 IIC1 Peripheral V25 D03 G04 F02 G02 G25 Interrupts AC12 H23 B24 D18 A19 V24 ...
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... PPC440GR Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 9 of 24) Signal Name MemData00 MemData01 MemData02 MemData03 MemData04 MemData05 MemData06 MemData07 MemData08 MemData09 MemData10 MemData11 MemData12 MemData13 MemData14 MemData15 MemData16 MemData17 MemData18 MemData19 MemData20 MemData21 MemData22 MemData23 MemData24 MemData25 MemData26 MemData27 ...
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... No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball 28 440GR – PPC440GR Embedded Processor Ball Interface Group AC14 D06 C06 A04 B07 NAND Flash AF14 AC16 AF17 AF18 F06 F07 F08 F09 F10 ...
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... PPC440GR Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 11 of 24) Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball ...
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... No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball 30 440GR – PPC440GR Embedded Processor Ball Interface Group J20 J21 K06 K07 K08 K09 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 ...
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... PPC440GR Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 13 of 24) Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball ...
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... No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball 32 440GR – PPC440GR Embedded Processor Ball Interface Group T09 T10 T17 T18 T19 T20 T21 U06 U07 U08 U09 U10 U11 U12 U13 U14 ...
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... PPC440GR Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 15 of 24) Signal Name No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball No ball ...
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... 440GR – PPC440GR Embedded Processor Ball Interface Group AA06 AA07 AA08 AA09 AA10 AA11 AA12 AA13 A physical ball does not exist at these ball coordinates. AA14 AA15 AA16 AA17 AA18 AA19 AA20 ...
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... PPC440GR Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 17 of 24) Signal Name PCIAD00 PCIAD01 PCIAD02 PCIAD03 PCIAD04 PCIAD05 PCIAD06 PCIAD07 PCIAD08 PCIAD09 PCIAD10 PCIAD11 PCIAD12 PCIAD13 PCIAD14 PCIAD15 PCIAD16 PCIAD17 PCIAD18 PCIAD19 PCIAD20 PCIAD21 PCIAD22 PCIAD23 PCIAD24 PCIAD25 PCIAD26 PCIAD27 ...
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... PCIGnt4 PCIGnt5 PCIIDSel PCIINT PCIIRDY PCIPar PCIPErr PCIReq0/Gnt PCIReq1 PCIReq2 PCIReq3 PCIReq4 PCIReq5 PCIReset PCISErr PCIStop PCITRDY 36 440GR – PPC440GR Embedded Processor Ball Interface Group D17 L24 A25 PCI D25 H25 E24 G26 PCI D20 PCI E25 PCI C23 PCI D24 ...
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... PPC440GR Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 19 of 24) Signal Name [PerAddr02]GPIO05[EOT3/TC3] [PerAddr03]GPIO04[DMAAck3] [PerAddr04]GPIO03[DMAReq3] [PerAddr05]GPIO02[EOT2/TC2] [PerAddr06]GPIO01[DMAAck2] [PerAddr07]GPIO00[DMAReq2] PerAddr08 PerAddr09 PerAddr10 PerAddr11 PerAddr12 PerAddr13 PerAddr14 PerAddr15 PerAddr16 PerAddr17 PerAddr18 PerAddr19 PerAddr20 PerAddr21 PerAddr22 PerAddr23 PerAddr24 PerAddr25 PerAddr26 PerAddr27 PerAddr28 PerAddr29 ...
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... PerData11 PerData12 PerData13 PerData14 PerData15 [PerErr]GPIO11 PerOE PerReady PerR/W PerWBE0 PerWBE1 PSROOut RAS [RcvrInh]HoldReq RefEn RejectPkt[DrvrInh1] 38 440GR – PPC440GR Embedded Processor Ball Interface Group H01 K04 G01 J03 J04 H03 E01 G03 External Slave Peripheral H04 E02 D01 F03 C01 F04 ...
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... PPC440GR Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 21 of 24) Signal Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SAGND SAV DD SCPClkOut[IIC1SClk] SCPDI[IIC1SData] SCPDO AMCC Proprietary Revision 1.19 – ...
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... SV REF2A SV REF2B SysClk SysErr SysReset TCK TDI TDO TestEn TmrClk1 TmrClk2 TMS [TrcBS0]GPIO49 [TrcBS1]GPIO50 [TrcBS2]GPIO51 TrcClk 40 440GR – PPC440GR Embedded Processor Ball Interface Group P05 R11 R16 T12 T15 W05 W22 Y05 Y22 Power AA05 AA22 AB06 AB07 AB08 AB14 AB19 ...
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... PPC440GR Embedded Processor Table 5. Signals Listed Alphabetically (Sheet 23 of 24) Signal Name [TrcES0]GPIO52 [TrcES1]GPIO53 [TrcES2]GPIO54 [TrcES3]GPIO55 [TrcES4]GPIO56 [TrcTS0]GPIO57 [TrcTS1]GPIO58 [TrcTS2]GPIO59 [TrcTS3]GPIO60 [TrcTS4]GPIO61 [TrcTS5]GPIO62 [TrcTS6]GPIO63 TRST [UART0_CTS/UART3_Rx]GPIO36 [UART0_RTS/UART3_Tx]GPIO37 UART0_Rx UART0_Tx [UART0_DCD/UART1_CTS/UART2_Tx]GPIO34 [UART0_DSR/UART1_RTS/UART2_Rx]GPIO35 [UART0_DTR/UART1_Tx]GPIO38 [UART0_RI/UART1_Rx]GPIO39 UARTSerClk AMCC Proprietary Revision 1.19 – May 07, 2008 ...
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... 440GR – PPC440GR Embedded Processor Ball Interface Group E05 E10 E11 E12 E15 E16 E17 E22 K05 K22 L05 L22 M05 M22 M14 N12 Power P15 R05 R13 R22 ...
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... PPC440GR Embedded Processor In the following table, only the primary (default) signal name is shown for each pin. Multiplexed or multifunction signals are marked with an asterisk (*). To determine what signals or functions are multiplexed on those pins, look up the primary signal name in Table 5, Signals Listed Alphabetically. ...
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... E21 F21 DD V E22 F22 DD E23 PCIStop F23 E24 PCIGnt5 F24 E25 PCIIRDY F25 E26 PCIC3/BE3 F26 44 440GR – PPC440GR Embedded Processor Signal Name Ball Signal Name GND G01 PerData02 GPIO42* G02 IRQ3* PerData11 G03 PerData07 PerData13 G04 GPIO41 G05 DD ...
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... PPC440GR Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball J01 DM2 K01 J02 CAS K02 J03 PerData03 K03 J04 PerData04 K04 J05 GND K05 J06 No ball K06 J07 No ball K07 J08 No ball K08 J09 ...
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... N21 No ball P21 OV N22 P22 DD N23 PCIAD28 P23 N24 GPIO38* P24 N25 PCIReq0/Gnt P25 N26 PCIAD29 P26 46 440GR – PPC440GR Embedded Processor Signal Name Ball Signal Name MemAddr00 R01 BankSel2 ECC0 R02 BankSel1 SV R03 MemAddr10 REF2A MemAddr01 R04 BankSel0 SV V R05 ...
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... PPC440GR Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball U01 MemAddr04 V01 U02 MemData31 V02 U03 MemData29 V03 U04 MemAddr06 V04 V U05 V05 DD U06 No ball V06 U07 No ball V07 U08 No ball V08 U09 No ball ...
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... AA21 No ball AB21 SV AA22 AB22 DD AA23 GPIO31* AB23 AA24 GPIO51* AB24 AA25 GPIO30* AB25 AA26 GND AB26 48 440GR – PPC440GR Embedded Processor Signal Name Ball Signal Name SysErr AC01 GND MemAddr09 AC02 MemData20 GPIO54* AC03 MemData19 GPIO55* AC04 GND V AC05 MemData17 DD ...
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... PPC440GR Embedded Processor Table 6. Signals Listed by Ball Assignment (Sheet Ball Signal Name Ball AE01 GND AF01 AE02 GND AF02 AE03 MemData16 AF03 AE04 MemSelfRef AF04 AE05 DM0 AF05 SV AE06 AF06 REF2B AE07 MemData13 AF07 AE08 MemData11 AF08 AE09 ...
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... PPC440GR has control of the external bus. When during the course of normal chip operation an external master gains ownership of the external bus, these same pins are used as inputs which are driven by the external master and received by the EBC in the PPC440GR. In this example, the pins are also bidirectional, serving both as inputs 50 440GR – ...
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... PPC440GR Embedded Processor and outputs. Multimode Signals In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin has multiple signal names assigned to distinguish different modes of operation, all of the names are shown. Strapping Pins One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see “ ...
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... Configure EMAC1 to use internal clocks by setting SDR0_MFR[E1CS]=1 and reset EMAC1 by setting EMAC0_MR1[SRST]=1. – No pull ups or downs required. Oddities: TmrClk2 must be connected to a clock to ensure reset of internal logic. It can be connected to any available clocks in the frequency range of 32kHz to 100MHz. 52 440GR – PPC440GR Embedded Processor Ω resistors to +3.3v. 3k Ω resistor to GND. 1k Ω resistors to +3.3v. 3k ...
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... PPC440GR Embedded Processor Table 9. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ to 3.3V not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
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... Memory address bus. MemClkOut0 Subsystem clock. MemClkOut0 MemData00:31 Memory data bus. MemSelfRef Self refresh. RAS Row Address Strobe. WE Write Enable. S SSTL reference voltage. VREF1 S Supplemental SSTL reference voltage. VREF2A:B 54 440GR – PPC440GR Embedded Processor Description I I Type Notes 2 ...
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... PPC440GR Embedded Processor Table 9. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ to 3.3V not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
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... Note: PerData00 is the most significant bit (msb) on this bus. Used by either peripheral controller or DMA controller depending upon the type of transfer involved. When the PerOE PPC440GR is the bus master, it enables the selected device to drive the bus. Used by a peripheral slave to indicate it is ready to transfer PerReady data ...
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... If not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset; pull-up or pull-down required Signal Name External Master Peripheral Interface Bus Request. Used when the PPC440GR needs to regain BusReq control of peripheral interface from an external master. External Acknowledgement. Used by the PPC440GR to ExtAck indicate that a data transfer occurred ...
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... Test Data Out. TMS Test Mode Select. Test Reset. Note: Must be asserted low during a power-on system reset in TRST order to reset the JTAG interface. If the JTAG interface is not reset, the processor may not boot. 58 440GR – PPC440GR Embedded Processor Description I ...
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... PPC440GR Embedded Processor Table 9. Signal Functional Description (Sheet Notes: 1. Receiver input has hysteresis 2. Must pull up (recommended value is 3kΩ to 3.3V) 3. Must pull down (recommended value is 1kΩ not used, must pull up (recommended value is 3kΩ to 3.3V not used, must pull down (recommended value is 1kΩ) 6. Strapping input during reset ...
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... PLL (analog) voltage ground. SAV 1.5V—Filtered voltage for memory PLL (analog). DD SAGND PLL (analog) memory voltage ground. Other To avoid noise pickup problems, most of these balls must be Reserved connected in the board design as shown Table 8 on page 51. 60 440GR – PPC440GR Embedded Processor Description I/O I/O O I/O I ...
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... PPC440GR Embedded Processor Device Characteristics Table 10. Absolute Maximum Ratings The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device. None of the performance specification contained in this document are guaranteed when operating at these maximum ratings ...
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... Input Leakage Current (No pull-up or pull-down) Input Leakage Current for Pull-Down Input Leakage Current for Pull-Up Input Max Allowable Overshoot (3.3V LVTTL) Input Max Allowable Undershoot (3.3V LVTTL) Output Max Allowable Overshoot (3.3V LVTTL) Output Max Allowable Undershoot (3.3V LVTTL) 62 440GR – PPC440GR Embedded Processor Symbol Minimum Typical V +1.4 +1 ...
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... DD 3. The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440GR. See “Absolute Maximum Ratings” on page 61. 4. Overshoot and undershoot voltages are for 10% duty cycle. 5. The time for overshoot or undershoot is time above OV Figure 4 ...
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... DD DD Analog Voltage Filter The analog voltages used for the on-chip PLLs can be derived from the logic voltage, but must be filtered before entering the PPC440GR. A separate filter, as shown below, is recommended for each voltage. • The filter should keep the AV DD mV. ...
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... PPC440GR Embedded Processor Table 13. Input Capacitance Parameter Group 1 (2.5V SSTL I/O) Group 2 (3.3V LVTTL I/O) Group 3 (PCI I/O) Group 4 (Receivers) Group 5 (3.3V tolerant CMOS I/O) Group 6 (USB) Table 14. Typical DC Power Supply Requirements +1.5V Supply Frequency (MHz) (V +AV +SAV DD DD 333 1.00 400 1.09 533 1.28 667 1.93 Notes: 1. Typical Power is based on nominal voltage of V application that exercises each core with representative traffic ...
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... Thermal resistance values for the E-PBGA package are as follows: Parameter Junction-to-ambient thermal resistance without heat sink Junction-to-ambient thermal resistance with heat sink Junction-to-case thermal resistance Junction-to-board thermal resistance 66 440GR – PPC440GR Embedded Processor Symbol Typical I 1250 ODD ...
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... PPC440GR Embedded Processor Table 17. Package Thermal Specifications Thermal resistance values for the E-PBGA package are as follows: Parameter Notes: 1. Case temperature measured at top center of case surface with device soldered to circuit board. C ×θ where T is ambient temperature and P is power consumption. ...
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... F C MAL Clock F Frequency C T Period C Figure 5. Timing Waveform SysClk is 2.5V/3.3V tolerant receiver. Slew rate should be measured between 0.7V and 1.7V. Note: 68 440GR – PPC440GR Embedded Processor Frequency 40% of nominal period 40% of nominal period 45% of nominal period CPU Frequency Min Max 333 667 33 ...
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... Ethernet operation is unaffected. 3. IIC operation is unaffected the system designer to ensure that any SSCG used with the PPC440GR meets the above Important: requirements and does not adversely affect other aspects of the system. AMCC Proprietary Revision 1.19 – ...
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... EMCTxClk input low time EMCRxClk input frequency MII EMCRxClk period MII EMCRefClk input frequency RMII (SMII) EMCRefClk period RMII (SMII) EMCRefClk input high time EMCRefClk input low time 70 440GR – PPC440GR Embedded Processor Min Max – 66.66 15 – 40% of nominal period 60% of nominal period ...
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... PPC440GR Embedded Processor Table 19. Peripheral Interface Clock Timings (Continued) Parameter EMCRxClk input high time EMCRxClk input low time PerClk (and OPB Clock) output frequency (for ext. master or sync. slaves) PerClk period PerClk output high time PerClk output low time ...
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... Revision 1.19 – May 07, 2008 Preliminary Data Sheet Figure 7. Output Delay and Float Timing Waveform Clock 1.25V max min Outputs OH High (Drive) Float (High-Z) Low (Drive) 72 440GR – PPC440GR Embedded Processor max min OH Valid max min OH Valid AMCC Proprietary ...
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... PPC440GR Embedded Processor Table 20. I/O Specifications—PCI, UART, IIC, SPI, Ethernet, System and Debug Interfaces (Sheet Notes: 1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard. 2. EMCSync is a weak driver. Redrive EMCSync when driving more than one load. Input (ns) ...
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... UARTn_RI UARTn_RTS Interrupts Interface IRQ0:9 JTAG Interface TCK TDI TDO TMS TRST System Interface SysReset Halt SysErr GPIO00:63 Trace Interface TrcClk TrcBS0:2 TrcES0:4 TrcTS0:6 74 440GR – PPC440GR Embedded Processor Output (ns) Valid Delay Hold Time min) (T max) (T min 3 3 ...
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... PPC440GR Embedded Processor Table 21. I/O Specifications—EBC, EBMI, DMA and NAND Flash Interfaces Notes: 1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns. Input (ns) Signal Setup Time Hold Time (T min External Slave Peripheral Interface ...
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... Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data not a recommended physical circuit design for this interface. An actual interface design will depend on many factors, including the type of memory used and the board layout. 76 440GR – PPC440GR Embedded Processor 10pF 120Ω 10pF ...
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... PPC440GR Embedded Processor Table 22. DDR SDRAM Output Driver Specifications Signal Path Write Data MemData00:07 MemData08:15 MemData16:23 MemData24:31 ECC0:7 DM0:8 MemClkOut0 MemAddr00:12 BA0:1 RAS CAS WE BankSel0:3 ClkEn0:3 DQS0:8 AMCC Proprietary Revision 1.19 – May 07, 2008 Preliminary Data Sheet Output Current (mA) I/O H (maximum) 15 ...
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... Hold time for data signals (minimum time data is valid after rising/falling edge of DSQ Delay from rising/falling edge of clock to the rising/falling edge of DQS DS The timing data in the following tables is based on simulation runs using Einstimer. Note: 78 440GR – PPC440GR Embedded Processor ...
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... PPC440GR Embedded Processor Table 23. I/O Timing—DDR SDRAM T Notes: 1. All of the DQS signals are referenced to MemClkOut0(0). 2. Clock speed is 133MHz. 3. The T values in the table include 3 cycle at 133MHz (7.5ns x 0.75 = 5.625 ns obtain adjusted values for lower clock frequencies, subtract 5.625 ns from the values in the table and add 3/4 of the cycle ...
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... In operation, following the receipt of an address and read command from the PPC440GR, the SDRAM generates data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GR using a DQS signal that is delayed 1 cycle. In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency ...
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... PPC440GR Embedded Processor Figure 11. DDR SDRAM Read Data Path Package pins Stage FF, Data XL C (SDRAM0_TR1[RDCT]) 1/4 Programmed Cycle DQS Read Clock Delay Delay PLB Clock FF Timing Input setup time = 0.2ns Input hold time = 0.1ns Propagation delay ( 0.4ns maximum P Table 26. I/O Timing— ...
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... Except for small, low frequency memory systems with the memory located physically close (1) to the PPC440GR unlikely that Stage 1 data can be sampled. When the data comes later necessary to sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing ...
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... PPC440GR Embedded Processor Example 2: In this example Read Clock is delayed almost 1/2 cycle. Without ECC, Stage 2 data can be sampled at is enabled, Stage 3 data must be sampled (see Example 3). In this example, T the software. Figure 13. DDR SDRAM Read Cycle Timing—Example 2 DQS at pin ...
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... Data in at RDSP with ECC Low High Data out RDSP with ECC Low T = Propagation delay from Stage 2 input to RDSP input w/o ECC Propagation delay from Stage 2 input to RDSP input with ECC TE 84 440GR – PPC440GR Embedded Processor ...
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... PPC440GR Embedded Processor Initialization The PPC440GR provides the option for setting initial parameters based on default values or by reading them from a slave PROM attached to the IIC0 bus (see “Serial EEPROM” below). Some of the default values can be altered by strapping on external pins (see “Strapping” below). ...
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... Correct description and move PerErr signal from master to slave. Change maximum VCO frequency to 1334MHz. 02/16/2006 1.14 Add revision level B (1.1) part numbers and PVR numbers. 05/24/2006 1.15 Update power dissipation and add additional temperature data. 07/19/2006 1.16 Correct enable/disable specifications for PCI Gnt/Req signals. 86 440GR – PPC440GR Embedded Processor Contents of Modification AMCC Proprietary ...
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... PPC440GR Embedded Processor Date Version Change analog voltage filter circuit inductor part number. Change all multiplexed GPIO signal defaults to the GPIO signals. Change AC12 default from IRQ5 to DMAReq1. Correct descriptions of LeakTest, RcvrInh, ModeCtrl, RefEn, and DrvrInh1:2 signals. Added Assembly Requirements section on page 17, added Unused I/Os section on page 50, placed the analog filter diagram in its own section ...
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... SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2006 Applied Micro Circuits Corporation. All Rights Reserved. 88 440GR – PPC440GR Embedded Processor Applied Micro Circuits Corporation http://www.amcc.com AMCC Proprietary ...