PPC440GR-3PBFFFCX AMCC [Applied Micro Circuits Corporation], PPC440GR-3PBFFFCX Datasheet - Page 55

• Manufacturer Part Number: PPC440GR-3PBFFFCX
• Description: Power PC 440GR Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

Table 7. Signal Functional Description (Sheet 6 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
AMCC Proprietary
440GR – PPC440GR Embedded Processor
NAND Flash Interface
NFALE
NFCE0:3
NFCLE
NFRdyBusy
NFREn
NFWEn
Serial Peripheral Interface
SCPClkOut
SCPDI
SCPDO
Interrupts Interface
IRQ0:4
IRQ5
IRQ6:9
JTAG Interface
TCK
TDI
TDO
TMS
TRST
Signal Name
Address Latch Enable.
External interrupt requests 0 through 4.
External interrupt request 5.
External interrupt requests 6 through 9.
Chip Enable (multiplexed with the PerCS0:3 signals).
Command Latch Enable.
Ready/Busy.
Indicates status of device during program erase or page read.
This signal is wire-or connected from all NAND Flash devices.
Read Enable strobe.
Write Enable strobe.
Clock output.
SCPClkOut, the serial port master clock out, is used to
synchronize all data movement both into and out of the device
through the serial data ports. Normally, data is shifted out on
the rising edge of the clock and shifted in on the negative
edge.
SCPClkOut is also used to shift data into and out of the slave
device. When the SPMODE register is reset, SCPClkOut is
forced to 0.
Data In.
Data is received from the connected slave device and is
captured synchronously with SysClk.
Data output.
Data is sent to the connected slave device synchronously with
SysClk.
Test Clock.
Test Data In.
Test Data Out.
Test Mode Select.
Test Reset.
Description
Preliminary Data Sheet
Revision 1.16 – July 19, 2006
I/O
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
3.3V tolerant
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
2.5V CMOS
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
w/pull-up
w/pull-up
w/pull-up
w/pull-up
Multiplex
Multiplex
Multiplex
Multiplex
Multiplex
Multiplex
Type
Notes
1, 5
1, 5
1, 5
1
1
5
4
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