PPC440GRX-NPAFFFTS AMCC [Applied Micro Circuits Corporation], PPC440GRX-NPAFFFTS Datasheet - Page 56

• Manufacturer Part Number: PPC440GRX-NPAFFFTS
• Description: PowerPC 440GRx Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

440GRx – PPC440GRx Embedded Processor
Table 9. Signal Functional Description (Sheet 1 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to OV
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to OV
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
56
PCI Interface
PCIAD00:31
PCIC0:3/BE0:3
PCIClk
PCIDevSel
PCIFrame
PCIGnt0/Req
PCIGnt1:5
PCIIDSel
PCIINT
PCIIRDY
PCIPar
PCIPErr
PCIReq0/Gnt
PCIReq1:5
PCIReset
PCISErr
PCIStop
PCITRDY
Signal Name
Address/Data bus (bidirectional).
Provides timing to the PCI interface for PCI transactions.
Even parity.
PCI Command/Byte Enables
Indicates the driving device has decoded its address as the
target of the current access.
(PCI 2.2 specification requires 8.2kΩ pull up on host system).
Driven by the current master to indicate beginning and
duration of an access.
(PCI 2.2 specification requires 8.2kΩ pull up on host system).
Indicates that the specified agent is granted access to the
bus. When the internal arbiter is enabled, output is PCIGnt0.
When the internal arbiter is disabled, output is Req.
Indicates that the specified agent is granted access to the
bus. Used only when internal PCI arbiter enabled.
Used as a chip select during configuration read and write
transactions.
Level sensitive PCI interrupt.
Indicates initiating agent’s ability to complete the current data
phase of the transaction.
(PCI 2.2 specification requires 8.2kΩ pull up on host system).
Reports data parity errors during all PCI transactions except a
Special Cycle.
(PCI 2.2 specification requires 8.2kΩ pull up on host system).
Indicates to the PCI arbiter that the specified agent wishes to
use the bus. When the internal arbiter is enabled, input is
PCIReq0. When internal arbiter is disabled, input is Gnt.
An indication to the PCI arbiter that the specified agent wishes
to use the bus. Used only when internal PCI arbiter enabled.
Brings PCI device registers and logic to a consistent state.
Reports address parity errors, data parity errors on the
Special Cycle command, or other catastrophic system errors.
(PCI 2.2 specification requires 8.2kΩ pull up on host system).
Indicates the current target is requesting the master to stop
the current transaction.
(PCI 2.2 specification requires 8.2kΩ pull up on host system).
I
data phase of the transaction.
(PCI 2.2 specification requires 8.2kΩ pull up on host system).
ndicates the target agent’s ability to complete the current
DD
(EOV
Description
.
DD
DD
for Ethernet)
(EOV
DD
for Ethernet)
Revision 1.08 – October 15, 2007
Preliminary Data Sheet
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
3.3V PCI
Type
AMCC Proprietary
Notes
1, 5
1, 4
1, 4