PPC440GX-3FF533C AMCC [Applied Micro Circuits Corporation], PPC440GX-3FF533C Datasheet - Page 53

• Manufacturer Part Number: PPC440GX-3FF533C
• Description: Power PC 440GX Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

Revision 1.15 – August 30, 2007
Signal Functional Description
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
AMCC
GMCCrS,
GMC1TxClk,
RTBI1TxClk
GMCRefClk
GMCRxD0:3,
GMC0RxD0:3,
TBIRxD0:3,
RTBI0RxD0:3
GMCRxD4:7,
GMC1RxD0:3,
TBIRxD4:7,
RTBI1RxD0:3
GMCRxDV,
GMC0RxCtl,
TBIRxD8,
RTBI0RxD4
GMCRxEr,
GMC1RxCtl,
TBIRxD9,
RTBI1RxD4
GMCTxEn,
GMC0TxCtl,
TBITxD8,
RTBI0TxD4
GMCTxEr,
GMC1TxCtl,
TBITxD9,
RTBI1TxD4
GMCTxClk
TBIRxClk1
External Slave Peripheral Interface
DMAAck0:3
DMAReq0:3
EOT0:3/TC0:3
PerAddr00:31
PerWBE0:3
PerBLast
PerCS0:7
PerData00:31
Data Sheet
Signal Name
GMII: Carrier sense
RGMII: Transmit clock
RTBI: Transmit clock
GMII, RGMII, TBI and RTBI: Gigabit reference clock
GMII: Receive data
RGMII: Receive data
TBI: Receive data
RTBI: Receive data
GMII: Receive data
RGMII: Receive data
TBI: Receive data
RTBI: Receive data
GMII: Receive data valid
RGMII: Receive control
TBI: Receive data
RTBI: Receive data
GMII: Receive error
RGMII: Receive control
TBI: Receive data
RTBI: Receive data
GMII: Transmit data enable
RGMII: Transmit control
TBI: Transmit data
RTBI: Transmit data
GMII: Transmit error
RGMII: Transmit control
TBI: Transmit data
RTBI: Transmit data
GMII: 10/100Mbps Transmit clock
TBI: Receive clock 1
Used by the PPC440GX to indicate that data transfers have
occurred.
Used by slave peripherals to indicate they are prepared to transfer
data.
End Of Transfer/Terminal Count.
Peripheral address bus used by PPC440GX when not in external
master mode, otherwise used by external master.
Note: PerAddr00 is the most significant bit (msb) on this bus.
External peripheral data bus byte enables.
Used by either the peripheral controller, DMA controller, or
external master to indicates the last transfer of a memory access.
External peripheral device select.
Peripheral data bus used by PPC440GX when not in external
master mode, otherwise used by external master.
Note: PerData00 is the most significant bit (msb) on this bus.
(Sheet 4 of 8)
Description
440GX – Power PC 440GX Embedded Processor
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V tolerant
3.3V tolerant
2.5V CMOS
2.5V CMOS
2.5V CMOS
2.5V CMOS
2.5V CMOS
2.5V CMOS
2.5V CMOS
2.5V CMOS
2.5V CMOS
2.5V CMOS
2.5V CMOS
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
Type
Notes
1, 5
1, 5
1, 2
1, 4
5
6
5
1
2
1
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