HYB5116405BJBT-50- SIEMENS [Siemens Semiconductor Group], HYB5116405BJBT-50- Datasheet - Page 11

• Manufacturer Part Number: HYB5116405BJBT-50-
• Description: 4M x 4-Bit Dynamic RAM 2k & 4k Refresh
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Notes:
1) All voltages are referenced to
2)
3)
4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during
5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has
6) AC measurements assume
7)
8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined
9) Operation within the t
10) Operation within the t
11) Either t
12) t
13) Either
14) Either
15) t
16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge
17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM
Semiconductor Group
operation:
If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR
refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh.
If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the
refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh
I
I
a hyper page mode (EDO) cycle
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
V
measured between
by the latter of t RAC , t CAC , t AA ,t CPA , t OEA . t CAC is measured from tristate.
only. If t
only. If t
referenced to output voltage levels. t
last.
electrical characteristics only. If t
open-circuit (high impedance) through the entire cycle; if t
the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above
sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate.
in read-write cycles.
OFF (max.)
WCS
CC1
CC1
IH
,
(min.)
, t
and
I
CC3
RWD
t
t
RCH
DZC
CDD
RCD
RAD
, t
,
and
I
CC4
, t
I
OEZ (max.)
CC4
or t
or
or
is greater than the specified t
is greater than the specified t
CWD
depend on output loading. Specified values are obtained with the output open.
V
t
t
and
RRH
DZO
ODD
IL (max.)
and t
must be satisfied for a read cycle.
must be satisfied.
must be satisfied.
I
define the time at which the output achieves the open-circuit conditions and are not
CC6
V
RCD (max.)
RAD (max.
IH
AWD
are reference levels for measuring timing of input signals. Transition times are also
depend on cycle rate.
and
are not restrictive operating parameters. They are included in the data sheet as
V
t
)
T
IL
limit ensures that t
limit ensures that t
V
= 2 ns.
.
SS
WCS
.
OFF
> t
WCS (min.)
is referenced from the rising edge of RAS or CAS, whichever occurs
RAD (max.)
RCD (max.)
, the cycle is an early write cycle and data out pin will remain
RAC (max.)
RAC (max.)
limit, then access time is controlled by t
limit, then access time is controlled by t
11
can be met. t
can be met. t
RWD
HYB5116(7)405BJ/BT-50/-60/-70
> t
RWD (min.)
RCD (max.)
RAD (max.)
, t
CWD
is specified as a reference point
is specified as a reference point
> t
4M x 4-EDO DRAM
CWD (min.)
AA
CAC
and t
.
.
AWD
> t
AWD (min.)
,