KMM366S403CTL SAMSUNG [Samsung semiconductor], KMM366S403CTL Datasheet - Page 10
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KMM366S403CTL
Manufacturer Part Number
KMM366S403CTL
Description
PC66 SDRAM MODULE
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.KMM366S403CTL.pdf
(11 pages)
KMM366S403CTL
SIMPLIFIED TRUTH TABLE
Notes :
Register
Refresh
Bank active & row addr.
Read &
column address
Write &
column address
Burst stop
Precharge
Clock suspend or
active power down
Precharge power down mode
DQM
No operation command
1. OP Code : Operand code
2. MRS can be issued only at both banks precharge state.
3. Auto refresh functions are as same as CBR refresh of DRAM.
4. BA
5. During burst read or write with auto precharge, new read/write command can not be issued.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
The automatical precharge without row precharge command is meant by "Auto".
If "Low" at read, write, row active and precharge, bank A is selected.
If "High" at read, write, row active and precharge, bank B is selected.
If A
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
A
A new command can be issued after 2 clock cycle of MRS.
Auto/self refresh can be issued only at both banks precharge state.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
0
~ A
0
10
: Bank select address.
/AP is "High" at row precharge, BA
10
Command
/AP, BA
Mode register set
Auto refresh
Self
refresh
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
Bank selection
Both banks
0
: Program keys. (@ MRS)
Entry
Entry
Entry
Exit
Exit
Exit
CKEn-1
0
H
H
H
H
H
H
H
H
H
H
H
is ignored and both banks are selected.
L
L
L
CKEn
X
H
H
X
X
X
X
X
H
H
X
L
L
L
R P
CS
H
H
H
H
H
X
L
L
L
L
L
L
L
L
L
L
L
L
after the end of burst.
RAS
H
H
H
H
H
H
L
L
X
L
L
X
V
X
X
X
V
X
X
CAS
H
H
H
H
H
H
X
X
V
X
X
X
V
X
L
L
L
L
(V=Valid, X=Don t care, H=Logic high, L=Logic low)
WE
H
H
H
H
H
H
X
X
V
X
X
X
V
X
L
L
L
L
PC66 SDRAM MODULE
DQM
X
X
X
X
X
X
X
X
X
X
X
X
V
X
BA
V
V
V
V
X
0
A
OP code
10
REV. 3 Mar. '98
Row address
H
H
H
L
L
L
/AP
X
X
X
X
X
X
X
A
(A
(A
Column
address
Column
address
9
0
0
X
~ A
~ A
~ A
8
8
0
)
)
Note
1,2
4,5
4,5
3
3
3
3
4
4
6
7