KMM366S403CTL SAMSUNG [Samsung semiconductor], KMM366S403CTL Datasheet - Page 7

• Manufacturer Part Number: KMM366S403CTL
• Description: PC66 SDRAM MODULE
• Manufacturer: SAMSUNG [Samsung semiconductor]

KMM366S403CTL
Notes :
AC OPERATING TEST CONDITIONS
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Output
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
(Fig. 1) DC output load circuit
and then rounding off to the next higher integer.
870
Parameter
Parameter
3.3V
1200
50pF
CAS latency=3
CAS latency=2
V
V
OH
OL
t
t
t
t
t
t
t
t
RAS
RRD
RCD
t
CCD
Symbol
t
RAS
RDL
CDL
BDL
RC
RP
(DC) = 0.4V, I
(DC) = 2.4V, I
(V
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
DD
= 3.3V
OL
OH
0.3V, T
= 2mA
= -2mA
A
= 0 to 70 C)
See Fig. 2
tr/tf = 1/1
2.4/0.4
Value
1.4
1.4
Version
Output
100
20
26
26
50
80
12
-0
1
1
1
2
1
PC66 SDRAM MODULE
(Fig. 2) AC output load circuit
Z0 = 50
REV. 3 Mar. '98
Unit
CLK
CLK
CLK
ea
ns
ns
ns
ns
us
ns
ns
Vtt = 1.4V
Unit
50
ns
50pF
V
V
V
Note
1
1
1
1
1
2
2
2
3
4