S5935TFC AMCC [Applied Micro Circuits Corporation], S5935TFC Datasheet - Page 132

• Manufacturer Part Number: S5935TFC
• Description: PCI Product
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

S5935 – PCI Product
132
In both cases, step 3 involves accessing the mailbox. To allow the incoming mailbox interrupt logic to be cleared, the mailbox
status bit must also be cleared. Reading an incoming mailbox clears the status bits. Another option for clearing the status bits
is to use the Mailbox Flag Reset bit in the MCSR and AGCSTS registers, but this clears all status bits, not just for a single
mailbox or mailbox byte. For outgoing mailbox interrupts, the read of a mailbox register is what generated the interrupt; this
ensures the status bits are already clear.
1. Identify the interrupt source(s). Multiple interrupt sources are available on the S5935. The interrupt service routine must
2. Check mailbox status. The mailbox status bits indicate which mailbox bytes must be read or written.
3. Access the mailbox. Based on the contents of AMBEF, mailboxes are read or written. Reading an incoming mailbox
4. Clear the interrupt source. The Add-On IRQ# signal is deasserted by clearing the interrupt request. The request is
AMBEF
AMBEF
AOMBx
AIMBx
AINT
AINT
AINT
AINT
verify that a mailbox generated the interrupt (and not some other interrupt source).
byte clears the corresponding status bit in AMBEF.
cleared by writing a ‘1’ to the appropriate bit.
DS1527
Bit 16
Bit 17
Bits 31:16
Bits 15:0
Bits 31:0
Bits 31:0
Bit 16
Bit 17
Servicing an Add-On mailbox interrupt (IRQ#):
Add-On incoming mailbox interrupt indicator
Add-On outgoing mailbox interrupt indicator
Empty Add-On outgoing mailbox bytes
Full Add-On incoming mailbox bytes
Add-On incoming mailboxes
Add-On outgoing mailboxes
Clear Add-On incoming mailbox interrupt
Clear Add-On outgoing mailbox interrupt
Revision 1.02 – June 27, 2006
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