S5935TFC AMCC [Applied Micro Circuits Corporation], S5935TFC Datasheet - Page 45

• Manufacturer Part Number: S5935TFC
• Description: PCI Product
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

S5935 – PCI Product
CACHE LINE SIZE REGISTER (CALN)
Figure 14. Cache Line Size Register
AMCC Confidential and Proprietary
Register Name
Address Offset
Power-up value
Boot-load
Attribute
Size
7
Cache Line Size
0Ch
00h, hardwired
not used
Read Only
8 bits
00h
This register is hardwired to 0. The cache line configu-
ration register is used by the system to define the
cache line size in doubleword (64-bit) increments. This
controller does not use the “Memory Write and Invali-
date” PCI bus cycle commands when operating in the
bus master mode, and therefore does not internally
require this register. When operating in the target
mode, this controller does not have the connections
necessary to “snoop” the PCI bus and accordingly
cannot employ this register in the detection of burst
transfers that cross a line boundary.
Revision 1.02 – June 27, 2006
Cache Line Size (RO)
Data Book
0
DS1527
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