K7R163684B_06 SAMSUNG [Samsung semiconductor], K7R163684B_06 Datasheet
K7R163684B_06
Related parts for K7R163684B_06
K7R163684B_06 Summary of contents
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... K7R163684B K7R161884B 18Mb QDRII SRAM Specification 165FBGA with Pb & Pb-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ...
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... SAMSUNG branch office near your office, call or contact Headquarters. 512Kx36 & 1Mx18 QDR SRAM From To 200 230 180 210 160 190 140 170 - SRAM Draft Date Remark Advance Oct. 17. 2002 Preliminary Dec. 16, 2002 Preliminary Dec. 26, 2002 Preliminary Jan. 27, 2003 Preliminary Mar. 20, 2003 Preliminary April. 4, 2003 Preliminary June ...
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... K K CLK GEN C C Notes: 1. Numbers are for x18 device QDR SRAM and Quad Data Rate comprise a new family of products developed by Cypress, Hitachi, IDT, Micron, NEC and Samsung technology. 512Kx36 & 1Mx18 QDR II b4 SRAM TM Organization X36 X18 * -E(F)C(I) E(F) [Package type] : E-Pb Free, F-Pb ...
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... D18:D26 and PIN NUMBERS 6B, 6A 6P, 6R 11A 7B,7A,5A,5B 2H,10H 11H 10R 11R 2R 1R 2A,3A,10A,6C,9A voltage. output impedance is set to minimum value and it cannot be connected to ground or left unconnected SRAM NC/SA* NC/SA D17 Q17 D16 Q16 ...
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... D9:D17. 1 PIN NUMBERS 6B, 6A 6P, 6R 11A 3F,2G,3J,3L,3M,2N 2F,3G,3K,2L,3N, 7B, 5A 2H,10H 11H 10R 11R 2R 1R voltage. output impedance is set to minimum value and it cannot be connected to ground or left unconnected SRAM NC/SA ...
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... Memory bandwidth is maximized as data can be transferred into SRAM on every rising edge of K and K, and transferred out of SRAM on every rising edge of C and C. And totally independent read and write ports eliminate the need for high speed bus turn around. ...
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... In all cases impedance updates are transparent to the user and do not produce access time “push-outs” or other anomalous behavior in the SRAM. There are no power up requirements for the SRAM. However, to guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles. ...
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... State machine control timing sequence is controlled by K. 512Kx36 & 1Mx18 QDR STATE DIAGRAM POWER-UP READ WRITE READ WRITE READ D count=2 D count=2 ALWAYS ALWAYS - SRAM WRITE NOP WRITE WRITE LOAD NEW D count=2 WRITE ADDRESS D count=0 ALWAYS DDR WRITE D count=D count+1 WRITE D count=1 INCREMENT WRITE ADDRESS ...
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... SRAM Q OPERATION Q(A2) Q(A3) Q(A4) Previous Previous Previous Clock Stop state state state High-Z High-Z High-Z No Operation OUT OUT OUT at C(t+2) at C(t+2) at C(t+ OPERATION WRITE ALL BYTEs ( K↑ ) WRITE ALL BYTEs ( K↑ ...
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... DD -16 I =-1.0mA OH I =1.0mA OL . DDQ ±50mV. The levels are defined separately for measuring REF +0.85V(pulse width ≤ 3ns). DDQ - SRAM RATING V -0 DDQ 0.3 IN DD+ T -65 to 150 STG OPR T - OPR ...
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... DDQ V REF V SS Symbol Value Unit V 1.7~1 1.4~1.9 V DDQ V /V 1.25/0. 0.75 V REF T /T 0.3/0 DDQ - SRAM =0°C to +70°C) A MIN MAX UNIT REF - V - 0.2 V REF or V IL(AC) IH(AC IL(DC) IH(DC -0.25V -0.5V 20% t (MIN) KHKH MIN MAX 1.7 1.9 1.4 1.9 0.68 ...
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... MAX parameter (worst case at 70°C, 1.7V not possible for two SRAMs on the same board such different voltage and temperature. 5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. ...
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... OUT OUT C - CLK =1.5V. DDQ SYMBOL θ JA θ R=250Ω SRAM REF - SRAM TYP MAX Unit NOTES TYP Unit NOTES °C 17.1 /W °C 3 SRAM ...
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... CHQV CHQX KHKH t t CHQV t CQHQV t t CQHQX CHCQV t CHCQX WRITE KLKH t KHKH t t AVKH KHAX A2 t KHIX D1-1 D1-2 D1-3 D1 SRAM NOP NOP Q1-4 Q2-1 Q2-2 Q2-3 CHCQV t CHCQX ′ Don t Care NOP D2-1 D2-2 D2-3 D2 DVKH KHDX ′ Don t Care Rev. 5.0 July 2006 Q2-4 t CHQZ Undefined NOP ...
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... R D(Data In) D(Data Out Note address A3=A2, data Q3-1=D2-1, data Q3-2=D2-2 , data Q3-3=D2-3, data Q3-4=D2-4 Write data is forwarded immediately as read results. 2.BWx (NWx) assumed active. 512Kx36 & 1Mx18 QDR WRITE READ A2 A3 D2-1 D2-2 Q1-1 Q1 SRAM WRITE NOP A4 D2-3 D2-4 D4-1 D4-2 Q1-3 Q1-4 Q3-1 Q3-2 ′ Don t Care Rev. 5.0 July 2006 NOP D4-3 Q3-3 Undefined ...
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... This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control. In conformance with IEEE 1149.1, the SRAM contains a TAP controller, Instruction Reg- ister, Bypass Register and ID register. The TAP controller has a standard 16-state machine that resets internally upon power-up, therefore, TRST signal is not required ...
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... SRAM Boundary Scan 107 bits 107 bits Start Bit(0) (11 ORDER PIN ...
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... Output High Voltage (I =-2mA) OH Output Low Voltage(I =2mA) OL Note: 1. The input level of SRAM pin is to follow the SRAM DC specification JTAG AC TEST CONDITIONS Parameter Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level Note: 1. See SRAM AC test output load on page 11. ...
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... Body, 1.0mm Bump Pitch, 11x15 Ball Array Symbol Value Units 13 ± 0 ± 0.1 B 1.3 ± 0.1 C 0.35 ± 0.05 D 512Kx36 & 1Mx18 QDR Note Symbol SRAM B Top View Side View D E Bottom View H ∅ Value Units Note 1.0 mm 14.0 mm 10.0 mm 0.5 ± 0.05 mm Rev. 5.0 July 2006 ...