K7R163684B_06 SAMSUNG [Samsung semiconductor], K7R163684B_06 Datasheet - Page 9

• Manufacturer Part Number: K7R163684B_06
• Description: 512Kx36 & 1Mx18 QDRTM II b4 SRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K7R163684B
K7R161884B
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
Notes: 1. X means “Don′t Care”.
WRITE TRUTH TABLE
Notes: 1. X means “Don′t Care”.
WRITE TRUTH TABLE
Notes: 1. X means “Don′t Care”.
Stopped
K
↑
↑
↑
K
↑
↑
↑
↑
↑
2. The rising edge of clock is symbolized by ( ↑ ).
3. Before enter into clock stop status, all pending read and write operations will be completed.
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
4. This table illustrates operation for x18 devices.
2. All inputs in this table must meet setup and hold time around the rising edge of input clock K or K ( ↑ ).
3. Assumes a WRITE cycle was initiated.
4. This signal was HIGH on previous K clock rising edge. Initiating consecutive READ or WRITE operations on consecutive K clock rising edges
5. If this signal was LOW to initiated the previous cycle, this signal becomes a don′t care for this operation however it is strongly recommended
K
↑
↑
↑
↑
is not permitted. The device will ignore the second request.
that this signal is brought HIGH as shown in the truth table.
H
L
R
X
H
4
5
K
↑
↑
↑
↑
↑
W
L
X
H
X
4
K
↑
↑
↑
↑
Previous
at K(t+1)
(x18)
(x36)
D(A1)
state
Din
BW
X
X
H
H
H
H
H
H
L
L
L
L
0
Previous
at K(t+1)
BW
D(A2)
state
H
H
H
H
L
L
L
L
Din
X
X
0
BW
H
H
H
H
H
H
L
L
L
L
1
D
Previous
at K(t+2)
D(A3)
state
Din
X
X
BW
BW
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
1
2
Previous
at K(t+2)
D(A4)
state
Din
512Kx36 & 1Mx18 QDR
- 9 -
X
X
BW
H
H
H
H
H
H
L
L
L
L
3
Previous
at C(t+1)
High-Z
Q(A1)
D
state
OUT
X
Previous
at C(t+2)
High-Z
Q(A2)
D
state
WRITE ALL BYTEs ( K↑ )
WRITE ALL BYTEs ( K↑ )
WRITE NOTHING ( K↑ )
WRITE NOTHING ( K↑ )
WRITE BYTE 2 and BYTE 3 ( K↑ )
WRITE BYTE 2 and BYTE 3 ( K↑ )
OUT
X
WRITE BYTE 0 ( K↑ )
WRITE BYTE 0 ( K↑ )
WRITE BYTE 1 ( K↑ )
WRITE BYTE 1 ( K↑ )
WRITE ALL BYTEs ( K↑ )
WRITE ALL BYTEs ( K↑ )
WRITE NOTHING ( K↑ )
WRITE NOTHING ( K↑ )
OPERATION
Q
WRITE BYTE 0 ( K↑ )
WRITE BYTE 0 ( K↑ )
WRITE BYTE 1 ( K↑ )
WRITE BYTE 1 ( K↑ )
Previous
at C(t+2)
High-Z
Q(A3)
D
state
OPERATION
OUT
X
Rev. 5.0 July 2006
at C(t+3)
TM
Previous
High-Z
Q(A4)
D
state
OUT
X
II b4 SRAM
OPERATION
No Operation
Clock Stop
Read
Write