H57V2582GTR-60J HYNIX [Hynix Semiconductor], H57V2582GTR-60J Datasheet - Page 21

• Manufacturer Part Number: H57V2582GTR-60J
• Description: 256Mb Synchronous DRAM based on 8M x 4Bank x8 I/O
• Manufacturer: HYNIX [Hynix Semiconductor]

CKE Enable(CKE) Truth TABLE
Note :
1. For the given current state CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. When exiting power down mode,
3. The address inputs depend on the command that is issued.
4. The Precharge Power Down mode, the Self Refresh mode, and the Mode Register Set can only be entered
5. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously.
Rev 1.0 / Aug. 2009
listed above
other than
Any State
Current
a NOP (or Device Deselect) command is required on the first positive edge of clock after CKE goes high.
from the all banks idle state.
When exiting deep power down mode, a NOP (or Device Deselect) command is required on the first positive edge of
clock after CKE goes high and is maintained for a minimum 200usec.
State
Previous
Cycle
H
H
L
L
CKE
Current
Cycle
H
H
L
L
CS
X
X
X
X
RAS
X
X
X
X
(Sheet 2 of 2)
CAS
Command
X
X
X
X
WE
X
X
X
X
BA0,
BA1
X
X
X
X
Synchronous DRAM Memory 256Mbit
ADDR
X
X
X
X
Refer to operations of
the Current State
Truth Table
Begin Clock Suspend
next cycle
Exit Clock Suspend
next cycle
Maintain Clock Suspend
H57V2582GTR-xxI Series
Action
Notes
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