MSP3411G Micronas, MSP3411G Datasheet - Page 15

• Manufacturer Part Number: MSP3411G
• Description: (MSP34x1G) Multistandard Sound Processor Family
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
2.7. SCART Signal Routing
2.7.1. SCART DSP In and SCART Out Select
The SCART DSP Input Select and SCART Output
Select blocks include full matrix switching facilities. To
design a TV set with four pairs of SCART-inputs and
two pairs of SCART-outputs, no external switching
hardware is required. The switches are controlled by
the ACB user register (see page 40).
2.7.2. Stand-by Mode
If the MSP 34x1G is switched off by first pulling
STANDBYQ low and then (after >1 s delay) switching
off the 5-V, but keeping the 8-V power supply (‘Stand-
by’-mode), the SCART switches maintain their posi-
tion and function. This allows the copying from
selected SCART-inputs to SCART-outputs in the TV
set’s stand-by mode.
In case of power on or starting from stand-by (switch-
ing on the 5-V supply, RESETQ going high 2 ms later),
all internal registers except the ACB register (page 40)
are reset to the default configuration (see Table 3–5 on
page 22). The reset position of the ACB register
becomes active after the first I
Baseband Processing part (subaddress 12
transmitting the ACB register first, the reset state can
be redefined.
MICRONAS INTERMETALL
2
C transmission into the
hex
). By
2.8. I
It is possible to route in an external coprocessor for
special effects, like surround processing and sound
field processing. Routing can be done with each input
source and output channel via the I
puts.
Two possible interface formats are supported:
1. The SONY format: I2S_WS changes at the word
2. The PHILIPS format: I2S_WS changes one I2S_CL
The I
1. I2S_DA_IN1, I2S_DA_IN2:
2. I2S_DA_OUT:
3. I2S_CL:
4. I2S_WS:
The MSP 34x1G normally serves as the master on the
I
lines are driven by the MSP 34x1G. In slave mode,
these lines are input to the MSP 34x1G and the master
clock is synchronized to 576 times the I2S_WS rate
(32 kHz). NICAM operation is not possible in this
mode.
All I
register (see page 28).
A precise I
page 70.
2
S interface. In this case, the clock and word strobe
boundaries.
period before the word boundaries.
For input, four channels (two channels per line,
2*16 bits) per sampling cycle (32 kHz) are transmit-
ted.
For output, two channels (2*16 bits) per sampling
cycle (32 kHz) are transmitted.
Gives the timing for the transmission of I
data (1.024 MHz).
The I2S_WS word strobe line defines the left and
right sample.
2
2
S options can be set by means of the MODUS
2
S Bus Interface
S bus interface consists of five pins:
2
S timing diagram is shown in Fig. 4–26 on
MSP 34x1G
2
S inputs and out-
2
S serial
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