MSP3411G Micronas, MSP3411G Datasheet - Page 16

• Manufacturer Part Number: MSP3411G
• Description: (MSP34x1G) Multistandard Sound Processor Family
• Manufacturer: Micronas

MSP 34x1G
2.9. ADR Bus Interface
For the ASTRA Digital Radio System (ADR), the
MSP 3401G, MSP 3411G and MSP 3451G performs
preprocessing such as carrier selection and filtering.
Via the 3-line ADR-bus, the resulting signals are trans-
ferred to the DRP 3510A coprocessor, where the
source decoding is performed. To be prepared for an
upgrade to ADR with an additional DRP board, the fol-
lowing lines of MSP 34x1G should be provided on a
feature connector:
– AUD_CL_OUT
– I2S_DA_IN1 or I2S_DA_IN2
– I2S_DA_OUT
– I2S_WS
– I2S_CL
– ADR_CL, ADR_WS, ADR_DA
For more details, please refer to the DRP 3510A data
sheet.
2.10.Digital Control I/O Pins and
The static level of the digital input/output pins
D_CTR_I/O_0/1 is switchable between HIGH and
LOW via the I
(see page 40). This enables the controlling of external
hardware switches or other devices via I
The digital input/output pins can be set to high imped-
ance by means of the MODUS register (see page 28).
In this mode, the pins can be used as input. The cur-
rent state can be read out of the STATUS register (see
page 29).
Optionally, the pin D_CTR_I/O_1 can be used as an
interrupt request signal to the controller, indicating any
changes in the read register STATUS. This makes poll-
ing unnecessary, I
minimum (see STATUS register on page 29 and
MODUS register on page 28).
16
Status Change Indication
2
C-bus by means of the ACB register
2
C bus interactions are reduced to a
2
C-bus.
2.11. Clock PLL Oscillator and Crystal Specifications
The MSP 34x1G derives all internal system clocks
from the 18.432-MHz oscillator. In NICAM or in I
Slave mode, the clock is phase-locked to the corre-
sponding source. Therefore, it is not possible to use
NICAM and I
For proper performance, the MSP clock oscillator
requires a 18.432-MHz crystal. Note that for the
phase-locked modes (NICAM, I
tighter tolerance are required.
Remark on using the crystal:
External capacitors at each crystal pin to ground are
required. They are necessary for tuning the open-loop
frequency of the internal PLL and for stabilizing the fre-
quency in closed-loop operation. The higher the
capacitors, the lower the resulting clock frequency.
The nominal free running frequency should match
18.432 MHz as closely as possible.
Clock
AUD_CL_OUT. This pin must be activated for this pur-
pose (see Table 3–9 on page 28).
measurements
2
S-Slave mode at the same time.
PRELIMINARY DATA SHEET
should
MICRONAS INTERMETALL
2
S-Slave), crystals with
be
done
at
2
pin
S-