LC89052TA-E SANYO [Sanyo Semicon Device], LC89052TA-E Datasheet - Page 15

• Manufacturer Part Number: LC89052TA-E
• Description: Digital Audio Interface Receiver
• Manufacturer: SANYO [Sanyo Semicon Device]

8.3.4 Clock system diagram
• This section shows the relationship between the two types of master clock and clock switching and dividing functions.
• The items in square brackets near the switch and function blocks are the names of write commands.
• Lock/Unlock is switched automatically according to the PLL lock/unlock state.
8.3.5 Point to notice when switching the clock source
• If an attempt is made to switch the clock source from PLL lock state (oscillator amplifier stopped) to XIN using
• To switch the clock source using OCKSEL while maintaining the state of the ERROR pin when the PLL is locked in
• Note that when the clock source is switched to XIN from the state where the oscillator amplifier is stopped with the
• When the CKOUT clock is supplied to XIN without using an oscillator or an external clock, the VCO free-running
OCKSEL when a mode in which the results of input fs calculation are reflected in the error flags is specified through
FLIMIT, an error signal (H) is temporarily placed at the ERROR pin though the continuity of the clock is preserved.
The reason for this follows. When the clock switching is carried out, the oscillator amplifier is activated and the input
fs calculation is restarted. At the same time, the old results of fs calculation are reset and consequently, a change in
the fs value is recognized when the old fs value is compared with the newly calculated fs value.
this mode setting, it is necessary to put the oscillator amplifier into the continuous mode using AMPCNT.
PLL circuit locked, output clocks whose source is XIN start outputting after the oscillator amplifier has started
operation. While the PLL is locked, clock source switching from XIN to PLL is carried out immediately. In both
cases, clock continuity is maintained.
frequency output from the CKOUT pin with the PLL unlocked is somewhere between 10M and 16MHz. Clock
signals created by dividing CKOUT are output from BCK and LRCK pins. However, these clock frequencies vary
depending on the LC89052TA-E sample and fluctuate depending on supply voltage and operating environments.
Therefore, the frequency is not fixed. You need to take care when using the CKOUT, BCK, and LRCK clocks while
the PLL circuit is unlocked.
RXIN
XIN
XOUT
[AMPOPR]
[AMPCNT]
[PLLOPR]
[PLLCK0]
[PLLCK1]
[XINSET]
(512/2fs)
[XISEL0]
[XISEL1]
[XISEL2]
(256fs)
(384fs)
(512fs)
PLL
Figure 8.5 Master Clock System Diagram
Lock/Unlock
LC89052TA-E
[OCKSEL]
[MCKHFO]
Divider
Divider
Divider
1/256
1/384
1/512
1/2
1/2
1/3
1/4
1/6
1/8
CKOUT
LRCK
BCK
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