LC89052TA-E SANYO [Sanyo Semicon Device], LC89052TA-E Datasheet - Page 20

• Manufacturer Part Number: LC89052TA-E
• Description: Digital Audio Interface Receiver
• Manufacturer: SANYO [Sanyo Semicon Device]

8.4.6 Output data switching (SDIN, DATAO)
• The DATAO pin outputs the demodulated data when the PLL circuit is locked and the SDIN input data when the PLL
• The data input to SDIN must be synchronized with CKOUT, BCK, and LRCK clocks when XIN is the clock source.
• The SDIN input data is output to DATAO by setting RDTSTA, regardless of the PLL circuit locked/unlocked state. In
• The DATAO output data can also be forcibly muted by setting RDTMUT. The muting processing is output in
• The DATAO output can also be muted in the PLL unlocked state by RDTSEL setup.
• These setups take priority in the following order: RDTSEL < RDTSTA < RDTMUT.
• When XIN is set to be the clock source with OCKSEL, the PLL circuit operates as long as PLL operation is not
8.4.7 Calculation of input data sampling frequency
• The input data sampling frequency is calculated using the XIN clock.
• Normally, in modes where the oscillator amplifier is automatically stopped when the PLL circuit is locked, the
• In continuous operation mode, the oscillator amplifier continuously repeats calculations.
• The calculation result can be read out from CCB address 0xEC or output registers DO4 to DO6. However, note that
• If a system where the XIN and CKOUT pins are connected and no oscillator is required is being setup, the fs
circuit is unlocked. This switching is performed automatically according to the locked/unlocked state of the PLL
circuit.
this case, the CKOUT, BCK, and LRCK clocks are also switched to the XIN clock source. The switch occurs in
synchronization with the LRCK edge after RDTSTA setup.
synchronization with the LRCK edge after RDTMUT setup.
stopped with PDOWN[1:0] or PLLOPR. In this mode the state of the PLL circuit is always output from the ERROR
pin. Information processed regardless of the PLL state can be read out over the microcontroller interface.
calculation is done during the error period associated with ERROR and completed, and the value is retained when the
oscillator amplifier is stopped. Therefore, after the calculation is confirmed, the value does not change until the PLL
circuit is unlocked.
while the PLL can synchronize with data of 32k to 192kHz, fs calculation mode can be selected from two modes: 32k
to 96kHz calculation mode and 64k to 192kHz calculation mode. These modes are switched by FS4XIN. It is not
possible to monitor the fs calculation result of 32k to 192kHz in the same mode.
calculation result will always be "out of range".
PLL locked state
ERROR
DATAO
Figure 8.9 Timing Chart for DATAO Output Data Switching (When RDTSEL is set to "0")
UGPI
SDIN data
UNLOCK
Muted
LC89052TA-E
UGPI : When the clock switching transition period signal is selected
LOCK
Demodulated data
Muted
UNLOCK
SDIN data
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