LC89052TA-E SANYO [Sanyo Semicon Device], LC89052TA-E Datasheet - Page 18

• Manufacturer Part Number: LC89052TA-E
• Description: Digital Audio Interface Receiver
• Manufacturer: SANYO [Sanyo Semicon Device]

8.4.4 Output data formats: special mode (DATAO)
• The output format of after-demodulation audio data must be set with OFSEL[2:0].
• In the format shown below, input data information except the audio data is output as well.
• BCK, LRCK, and DATAO are output in synchronization with the rising edge of CKOUT. DATAO is output in
• Generation of output data starts at the LRCK edge immediately after the ERROR output turns low.
• (3) as bi-phase data output, the input bi-phase data is output in synchronization with 128fs clock BCK and fs clock
• As for NRZ data output in (4), (5), 28bits are output. 4 bits of validity (V), user data (U), channel status (C) and also
• The low level is output all the time except for the effective bit length of the NRZ data output.
synchronization with the falling edge of BCK.
LRCK. However, BCK in PLL unlocked state is set to the 64fs clock.
preamble B (Z) plus 24 bits of LSB first audio data. H is output as Z bit in the frames (L-ch and R-ch) whose
preamble B is confirmed.
DATAO
DATAO
DATAO
LRCK
LRCK
LRCK
BCK
BCK
BCK
C
P
LSB
LSB
-24 bit-
-24 bit-
(5) : NRZ data LSB first left-justified output (OFSEL[2 : 0]=111)
LSB
Figure 8.7 Data Output Timing (Special Mode)
28 bits
28 bits
(3) : Biphase data output (OFSEL[2 : 0]=101)
(4) : NRZ data I
L-ch
MSB
L-ch
MSB V
L-ch
V
U C
U C
LC89052TA-E
MSB V
2
Z
Z
S output (OFSEL[2 : 0]=110)
U
C
P
LSB
LSB
-24 bit-
-24 bit-
LSB
28 bits
28 bits
R-ch
MSB
R-ch
MSB V
R-ch
Notice : "Z" means Preamble "B"
Notice : "Z" means Preamble "B"
V
U C
U C
MSB
Z
Z
V
U
C
P
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