K4X51163PE-L SAMSUNG [Samsung semiconductor], K4X51163PE-L Datasheet - Page 11

• Manufacturer Part Number: K4X51163PE-L
• Description: 32Mx16 Mobile DDR SDRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K4X51163PE - L(F)E/G
12. DC CHARACTERISTICS
Recommended operating conditions (Voltage referenced to V
NOTE :
1) It has +/- 5
2) DPD(Deep Power Down) function is an optional feature, and it will be enabled upon request.
3) IDD specifications are tested after the device is properly intialized.
4) Input slew rate is 1V/ns.
5) Definitions for IDD: LOW is defined as V
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
Deep Power Down Current
Please contact Samsung for more information.
Parameter
°C
tolerance.
HIGH is defined as V
STABLE is defined as inputs stable at a HIGH or LOW level ;
SWITCHING is defined as: - address and command: inputs changing between HIGH and LOW once per two clock cycles ;
Symbol
IDD2PS
IDD2NS all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
IDD3PS one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
IDD3NS one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH;
IDD4W
IDD2P
IDD2N
IDD3P
IDD3N
IDD4R
IDD0
IDD5
IDD6
IDD8
tRC=tRCmin; tCK=tCKmin; CKE is HIGH; CS is HIGH between valid commands;
address inputs are SWITCHING; data bus inputs are STABLE
all banks idle, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
address and control inputs are SWITCHING; data bus inputs are STABLE
one bank active, CKE is LOW; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
address and control inputs are SWITCHING; data bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
address and control inputs are SWITCHING; data bus inputs are STABLE
one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; I
address inputs are SWITCHING; 50% data change each burst transfer
one bank active; BL = 4; tCK = tCKmin ; continuous write bursts;
address inputs are SWITCHING; 50% data change each burst transfer
tRC = tRFCmin ; tCK = tCKmin ; burst refresh; CKE is HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
CKE is LOW; t CK = t CKmin ;
Extended Mode Register set to all 0’s;
address and control inputs are STABLE;
data bus inputs are STABLE
Deep Power Down Mode Current
IN
IN
≥
≤
0.9 * VDDQ ;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE.
0.1 * VDDQ ;
SS
Test Condition
= 0V, Tc = -25 to 85°C)
- 14 -
Internal TCSR
- G
- E
OUT
Full Array
Full Array
1/2 Array
1/4 Array
1/2 Array
1/4 Array
=0 mA
Mobile DDR SDRAM
DDR333 DDR266 Unit Note
45
140
115
150
300
270
255
250
220
205
70
15
25
20
8
1)
0.3
0.3
15
5
2
115
100
135
600
500
450
500
400
350
65
12
25
20
85
8
mA
mA
mA
mA
mA
mA
mA
June 2007
uA
uA
°C
2