GM71C17400C Hynix Semiconductor, GM71C17400C Datasheet - Page 8

• Manufacturer Part Number: GM71C17400C
• Description: 4/194/304 WORDS x 4 BIT CMOS DYNAMIC RAM
• Manufacturer: Hynix Semiconductor

Rev 0.1 / Apr’01
Notes:
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AC Measurements assume t
An initial pause of 200us is required after power up followed by a minimum of eight
initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-
RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS
refresh cycles are required.
Operation with the
reference point only; if
controlled exclusively by
Operation with the
reference point only; if
controlled exclusively by
Either t
Either t
V
transition times are measured between V
Assume that
recommended value shown in this table,
Measured with a load circuit equivalent to 2 TTL loads and 100pF. (V
Assume that
Assume that
Either
t
and are not referenced to output voltage levels.
t
data sheet as electrical characteristics only; if
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if
t
t
data read from the selected cell; if neither of the above sets of conditions is satisfied, the
condition of the data out (at access time) is indeterminate.
These parameters are referenced to CAS leading edge in early write cycles and to WE leading
edge in delayed write or read-modify-write cycles.
t
Access time is determined by the longest among
OFF
WCS
AWD
RASP
RWD
IH
(min) and V
(max) and
,
(min) and
>=
defines RAS pulse width in Fast page mode cycles.
t
RWD
t
ODD
DZO
RCH
t
RWD
,
or t
or
or t
t
CWD
(min),
t
t
t
RCD
RAD
t
RCD
DZC
CDD
RRH
t
t
,
OEZ
CPW
IL
t
>=
>=
<=
AWD
must be satisfied.
must be satisfied for a read cycles.
must be satisfied.
(max) are reference levels for measuring timing of input signals. Also,
(max) define the time at which the outputs achieve the open circuit condition
>=
t
t
t
t
t
t
RCD
RAD
CWD
RCD
RAD
RCD
t
and
CPW
(max) and
(max) and
(max) limit insures that
(max) limit insures that
(max) and
>=
t
t
RCD
RAD
t
t
(min), the cycle is a read-modify-write and the data output will contain
CAC
AA
t
t
CPW
T
CWD
.
=5ns.
is greater than the specified
.
is greater than the specified
are not restrictive operating parameters. They are included in the
(min), and
t
t
RCD +
t
RCD +
RAD
<=
t
t
IH
t
CAC
CAC
RAC
t
(min) and V
RAD
(max) >=
(max) <=
t
exceeds the value shown.
AWD
(max). If
t
t
t
WCS
RAC
RAC
t
>=
AA
>=
(max) can be met,
(max) can be met,
or
t
AWD
t
t
IL
t
RAD +
RAD +
t
WCS
(max).
CAC
t
RCD
(min), or
(min), the cycle is an early write cycle
t
t
or
t
t
RCD
RAD
AA
AA
or
t
(max).
(max).
ACP
(max) limit, then access time is
(max) limit, then access time is
t
RAD
.
GM71C(S)17400C/CL
is greater than the maximum
t
CWD
OH
t
t
RCD
RAD
= 2.4V, V
>=
(max) is specified as a
(max) is specified as a
t
CWD
(min),
OL
= 0.8V)
t
AWD
>=