GM71C17400C Hynix Semiconductor, GM71C17400C Datasheet - Page 9

• Manufacturer Part Number: GM71C17400C
• Description: 4/194/304 WORDS x 4 BIT CMOS DYNAMIC RAM
• Manufacturer: Hynix Semiconductor

GM71C(S)17400C/CL
18.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device. After RAS is reset, if t
>=t
, the I/O pin will remain open circuit (high
OEH
CWL
impedance); if t
< t
, invalid data will be out at each I/O.
OEH
CWL
19.
The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA
and CA
for the
0
1
4M x 4 are don't care during test mode. Test mode is set by performing a WE-and-CAS-before-
RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O
(I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data
output pin is a high state during test mode read cycle, then the device has passed. If they are not
equal, data output pin is a low state, then the device has failed. Refresh during test mode
operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test
mode and enter a normal operation mode, perform either a regular CAS-before-RAS refresh
cycle or RAS-only refresh cycle.
t
t
t
t
In a test mode read cycle, the value of
,
,
and
is delayed by 2ns to 5ns for the
20.
RAC
AA
CAC
ACP
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
Rev 0.1 / Apr’01