K9K1208U0M-YIB0 Samsung semiconductor, K9K1208U0M-YIB0 Datasheet - Page 2

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K9K1208U0M-YIB0

Manufacturer Part Number
K9K1208U0M-YIB0
Description
64M x 8 Bit NAND Flash Memory
Manufacturer
Samsung semiconductor
Datasheet
GND
K9K1208U0M-YCB0, K9K1208U0M-YIB0
CLE
ALE
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
NOTE : Connect all V
R/B
Vcc
Vss
64M x 8 Bit NAND Flash Memory
FEATURES
WE
WP
PIN CONFIGURATION
RE
CE
- Memory Cell Array : (64M + 2,048K)bit x 8bit
- Data Register : (512 + 16)bit x8bit
- Page Program : (512 + 16)Byte
- Block Erase : (16K + 512)Byte
- Random Access : 10 s(Max.)
- Serial Page Access : 60ns(Min.)
- Program time : 200 s(Typ.)
- Block Erase Time : 2ms(Typ.)
- Program/Erase Lockout During Power Transitions
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
- K9K1208U0M-YCB0/YIB0 :
Voltage Supply : 2.7V~3.6V
Organization
Automatic Program and Erase
528-Byte Page Read Operation
Fast Write Cycle Time
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
Reliable CMOS Floating-Gate Technology
Command Register Operation
Package :
48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)
10
12
13
14
15
16
17
18
19
20
21
22
23
24
11
1
2
3
4
5
6
7
8
9
Do not leave V
CC
Standard Type
12mm x 20mm
48-pin TSOP1
CC
and V
or V
SS
SS
disconnected.
pins of each device to common power supply outputs.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
N.C
N.C
N.C
Vcc
Vss
N.C
N.C
N.C
I/O3
I/O2
I/O1
I/O0
N.C
N.C
N.C
N.C
2
GENERAL DESCRIPTION
The K9K1208U0M are a 64M(67,108,864)x8bit NAND Flash
Memory with a spare 2,048K(2,097,152)x8bit. Its NAND cell
provides the most cost-effective solution for the solid state
mass storage market. A program operation programs the 528-
byte page in typically 200 s and an erase operation can be per-
formed in typically 2ms on a 16K-byte block. Data in the page
can be read out at 60ns cycle time per byte. The I/O pins serve
as the ports for address and data input/output as well as com-
mand inputs. The on-chip write controller automates all pro-
gram and erase functions including pulse repetition, where
required, and internal verify and margining of data. Even the
write-intensive
K9K1208U0M s extended reliability of 100K program/erase
cycles by providing ECC(Error Correcting Code) with real time
mapping-out algorithm. The K9K1208U0M-YCB0/YIB0 is an
optimum solution for large nonvolatile storage applications such
as solid state file storage and other portable applications requir-
ing non-volatility.
PIN DESCRIPTION
Pin Name
I/O
GND
0
CLE
ALE
R/B
V
V
N.C
WE
WP
CE
RE
~ I/O
CC
SS
7
systems
Data Input/Outputs
Command Latch Enable
Address Latch Enable
Chip Enable
Read Enable
Write Enable
Write Protect
GND input for enabling spare area
Ready/Busy output
Power
Ground
No Connection
FLASH MEMORY
can
Pin Function
take
advantage
of
the

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