MAS9191AJ MAS [Micro Analog systems], MAS9191AJ Datasheet - Page 13

• Manufacturer Part Number: MAS9191AJ
• Description: Single Chip AMPS/ETACS/NAMPS Audio/Data Processor
• Manufacturer: MAS [Micro Analog systems]

FUNCTIONS
◆
After a reset the TX block is in power down. The
power down mode is controlled by bit TXSIP (TX
section in power down) in register 07
bit located in register 12
collision occurs or for any other TX block reset
causes. When the device is ready to receive data,
the TXWRD bit of register 10
are written into register 19
begins. The data is transferred from the serial
interface to the TX buffer and the TXWRD bit is set
high again, which causes XINT to become active.
The framing block adds bit sync (101010...10) and word sync (11100010010) sequences to the frames and
performs needed repeats depending on the mode.
Reverse control channel data format. The numbers under the frames show the number of bits in each section.
Reverse voice channel data format.
The Manchester encoder block encodes the data into
a Manchester coded format with bit clock. The bit
clock is 8kHz in the ETACS mode and 10kHz in the
AMPS mode. The mode can be controlled by bit
SYS0 of register 12
inverted with bit INVTX of register 13
bit does not go active between 56 and 104 bits of the
transmitted message a transmission collision occurs.
In this case the data which is in the TX block and the
data that the user is writing to the device will not be
Data Transmission
Bit sync
30
Bit Sync
Bit Sync
Bit Sync
101
37
37
HEX
Word sync
. The data polarity can be
HEX
Word
Word
Word
Sync
Sync
Sync
11
11
11
11
HEX
is used every time a TX
HEX
the data transmission
is high. If five bytes
1.Repeat
of word 1
5.Repeat
of word 1
5.Repeat
of word 2
DCC(1:0)
HEX.
HEX
48
48
48
00
01
10
11
.If the BUSY
The TXRST
Coded DCC
7
Bit Sync
Bit Sync
37
37
repeated 5 times
Word
Word
Sync
Sync
When the block comes out of power down mode the
XINT is active because the device is ready to receive
data (TXWRD goes high). The lower nibble of the
fifth byte is ignored. The 36 bits of data are coded by
the BCH coder with following polynomial:
The BCH coder adds 12 parity bits to the data and
the data is transferred to the DCC coding block. The
DCC coder adds a digital color code on the reverse
control channel (RECC) according following table.
transmitted. The TXCOL bit of register 10
high in this case and cause an interrupt. The TXCOL
will remain active until the TX block is reset with the
TXRST bit of register 12
active in register 12
transmitter off when a TX collision occurs. If the
AUMUT bit in register 13
audio block is muted with switch S19 on the voice
channel while data transmission is occurring.
11
11
First word
240
Coded DCC
G(x) = x
0000000
0011111
1100011
1111100
of word 1
of word 2
2.Repeat
1.Repeat
48
48
repeated 5 times
12
Second word
+ x
HEX
Bit Sync
Bit Sync
10
240
37
37
the TXCTRL output turns the
+ x
HEX
HEX
8
. If the TXCTREN bit is
+ x
is set to high the TX
5
+ x
Word
Word
Sync
Sync
11
11
4
DA9191A.000
July 31, 1997
+ x
3
+ x
HEX
0
will go
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