HMS87C5216 ETC1 [List of Unclassifed Manufacturers], HMS87C5216 Datasheet - Page 53

• Manufacturer Part Number: HMS87C5216
• Description: CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER FOR UR(Universal Remocon) & WIRELESS KEYBOARD
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

*Interrupt preprocess step is 8 machine cycle
(3) The valid timing after executing Interrupt control instructions
I flag is valid just after executing of EI/DI on the contrary.
terrupt Enable register is valid one instruction after controlling in-
13.4 INTERRUPT PROCESSING SEQUENCE
When an interrupt is accepted, the on-going process is stopped
and the interrupt service routine is executed. After the interrupt
service routine is completed it is necessary to restore everything
to the state before the interrupt occured.As soon as an interrupt is
accepted, the content of the program counter and PSW are save-
din the stack area. At the same time, the content of the vector ad-
dress corresponding to the accepted interrupt, which is in the
interrupt vector table, enters into the program counter and inter-
rupt service is executed. In order to execute the interrupt service
routine, it is necessary to write the jump addresses in the vector
table (FFE0 h ~ FFFF h) corresponding to each interrupt
13.5 SOFTWARE INTERRUPT (Interrupt by Break (BRK) Instruction)
Software interrupt is available just by writing ``Break(BRK)`` in-
struction. The values of PC and PSW is stacked by BRK instruc-
SEP. 2004 Ver 1.01
-Maximum 12 machine cycle (When execute DIV
-Minimum 0 machine cycle
Figure 13-3 Interrupt Procesing Step Timing
instruction)
addr bus
data bus
internal
internal
internal
internal
WRITE
READ
SYNC
clock
R/W
CODE
OP
↑
PC
CODE
↑
OP
SP
Interrupt Process Step
PCH
↑
SP-1
PCL
↑
PSW
↑
SP-2
In-
LVA
*2
vector
``L``
*Interrupt overhead
terrupt Enable Register.
* Interrupt Processing Step
1) Store upper byte of Program Counter, SP <= SP
2) Store lower byte of Program Counter, SP <= SP - 1
3) Store Program Status Word, SP <= SP - 2
4) After resetting of I-flag, clear accepted Interrupt Request Flag.
(Set B-flag for BRK Instruction)
5) Call Interrupt service routine
↑
tion and then B flag of PSW is set and I flag is reset.
-Maximum 1 + 12 + 8 = 21 machine cycle
-Minimum 1 + 0 + 8 = 9 machine cycle
HVA
*3
vector
``H``
↑
new PC
ISR
*1
*1 ISR
*2 LVA
*3 HVA
: Interrupt Service
: Low Vector Address
: High Vector Address
Routine
HMS87C5216