EM78P153EN EMC [ELAN Microelectronics Corp], EM78P153EN Datasheet
EM78P153EN
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EM78P153EN Summary of contents
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GENERAL DESCRIPTION EM78P153E is an 8-bit microprocessor with low-power and high-speed CMOS technology equipped with a 512*13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a PROTECTION bit to prevent intrusion of user’s code in ...
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FEATURES • 14-lead packages : EM78P153E • Operating voltage range : 2.3V~5.5V • Available in temperature range: 0 C~70 C • Operating frequency rang (base on 2 clocks ): * Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz ...
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... Package types pin DIP 300mil: EM78P153EP * 14 pin SOP 150mil: EM78P153EN • The transient point of system frequency between HXT and LXT is around 400KHz. This specification is subject to change without prior notice. 3 EM78P153E OTP ROM 2002/03/01 ...
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PIN ASSIGNMENTS P65/OSCI P64/OSCO P63//RST Table 1 Pin Description Symbol Pin No. Type Vdd 4 P65/OSCI 5 I/O P64/OSCO 6 I/O P63/RESET 7 P62/TCC 8 I/O P61 ...
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P66, P67 2, 3 I/O P50~P52 1,14,13 I/O P53 12 I/O VSS 11 This specification is subject to change without prior notice. * Wake up from sleep mode when the status of the pin changes. * Schmitt Trigger input during ...
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FUNCTION DESCRIPTION OSCO OSCI /RESET WDT timer Oscillator/Timing Control Prescaler Built-in RAM OSC R3 4.1 Operational Registers 1. R0 (Indirect Addressing Register not a physically implemented register. Its major function indirect addressing pointer. ...
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R2 (Program Counter) & Stack • Depending on the device type, R2 and hardware stack are 9-bit wide. The structure is depicted in Fig.3. • 512 13 bits on-chip OTP ROM addresses to the relative p rogramming instruction codes. ...
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R3(Status R5(Port5) 06 R6(Port6 R10 ...
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R3 (Status Register RST GP1 • Bit 0 (C) Carry flag • Bit 1 (DC) Auxiliary carry flag • Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is ...
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Bits Not used. • RF can be cleared by instruction but cannot be set. • IOCF is the interrupt mask register. • Note that the result of reading RF is the "logic AND" and ...
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ENI/RETI instructions • Bit 7 Not used. • CONT register is both readable and writable. 3. IOC5 ~ IOC6 (I/O Port Control Register) • "1" put the relative I/O pin into high impedance, while "0" defines the ...
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IOCC Register is both readable and writable. 6. IOCD (Pull-high Control Register /PH7 /PH6 • Bit 0 (/PH0) Control bit used to enable the pull-high of P60 pin. 0: Enable internal pull-high 1: Disable internal pull-high • ...
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TCIF interrupt • Bit 1 (ICIE) ICIF interrupt enable bit. 0: disable ICIF interrupt 1: enable ICIF interrupt • Bit 2 (EXIE) EXIF interrupt enable bit. 0: disable EXIF interrupt 1: enable EXIF interrupt • Bits 3~7 Not ...
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I/O Ports The I/O registers, both Port 5 and Port 6, are bi-directional tri-state I/O ports. Port 6 can be pulled-high internally by software except P63. In addition, Port 6 can also have open-drain output by software except P63. ...
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PORT Fig. 6 The Circuit of I/O Port and I/O Control Register for Port 5 P60 /INT PORT Bit 6 of IOCE CLK *Pull-high (down), Open-drain are not shown in the figure. ...
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P61~P67 PORT *Pull-high (down), Open-drain are not shown in the figure. Fig. 8 The Circuit of I/O Port and I/O Control Register for P61~P67 IOCE.1 D CLK T10 T11 T17 /SLEP Fig. 9 Block Diagram of I/O Port 6 with ...
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Table 2 Usage of Port 6 Input Change Wake-up/Interrupt Function (I) Wake-up from Port 6 Input Status Change (a) Before SLEEP 1. Disable WDT 2. Read I/O Port 6 (MOV R6,R6) 3. Execute "ENI" or "DISI" 4. Enable interrupt (Set ...
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The sleep (power down) mode is attained by executing the “SLEP” instruction. While entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller can be awakened by (1) External reset input on /RESET pin, (2) WDT ...
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Table 3 The Summary of the Initialized Values for Registers Address Name N/A IOC5 Wake-Up from Pin Change N/A IOC6 Wake-Up from Pin Change 0x05 P5 Wake-Up from Pin Change 0x06 P6 Wake-Up from Pin Change N/A CONT Wake-Up from ...
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Address Name Wake-Up from Pin Change 0x0C IOCC Wake-Up from Pin Change 0x0D IOCD Wake-Up from Pin Change 0x0E IOCE Wake-Up from Pin Change 0x0F IOCF Wake-Up from Pin Change 0x10~0x2F R10~R2F Wake-Up from Pin Change X: not used. U: ...
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Table 4 The Values of RST, T and P after RESET Reset Type Power on /RESET during Operating mode /RESET wake-up during SLEEP mode WDT during Operating mode WDT wake-up during SLEEP mode Wake-Up on pin change during SLEEP mode ...
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Interrupt The EM78P153E has three falling-edge interrupts as listed below: (1) TCC overflow interrupt (2) Port 6 Input Status Change Interrupt (3) External interrupt [(P60, /INT) pin]. Before the Port 6 Input Status Changed Interrupt is enabled, reading Port ...
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VCC /IRQn CLK /RESET 4.7 Oscillator 1. Oscillator Modes The EM78P153E can be operated in four different oscillator modes, such as Internal RC oscillator mode (IRC), External RC oscillator mode (ERC), ...
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Table 7 The Summary of Maximum Operating Speeds Conditions Two cycles with two clocks 2. Crystal Oscillator/Ceramic Resonators(XTAL) EM78P153E can be driven by an external clock signal through the OSCI pin as shown in Fig. 12. In most applications, pin ...
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Table 8 Capacitor Selection Guide for Crystal Oscillator or Ceramic Resonator Oscillator Type Ceramic Resonators Crystal Oscillator OSCI EM78P153E Fig. 14 Circuit for Crystal/Resonator-Series Mode EM78P153E Fig. 15 Circuit for Crystal/Resonator-Parallel Mode This specification is subject to change without prior ...
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External RC Oscillator Mode For some applications that do not need to have its timing to be calculated precisely, the RC oscillator (Fig. 16) offers a lot of cost savings. Nevertheless, it should be noted that the frequency of ...
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Table 9 RC Oscillator Frequencies Cext 20 pF 100 pF 300 pF <Note> 1. Measured on DIP packages. 2. Design reference only. 4. Internal RC Oscillator Mode EM78P153E offers a versatile internal RC mode with default frequency value of 4MHz. ...
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Word 0 Bit12~Bit0 Code Option Register (Word 0) Bit12 Bit11 Bit10 /RESET /ENWDT CLKS • Bit 12 (/RESET): Define pin7 as a reset pin. 0: /RESET enable 1: /RESET disable • Bit 11 (/ENWTD): Watchdog timer enable ...
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RC mode set-up time always 135ns. • Bit 4 (Type): Reserved. The bit4 set to “0” all the time. • Bit 3 (RCOUT): A selecting bit of High or Low frequency for internal RC Oscillator. RCOUT 0 1 • ...
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EM78P153E is equipped with Power On Voltage Detector (POVD) with a detecting level of 2.0 V. The extra external reset circuit will work well if Vdd rises quick enough ( less). In many critical applications however, extra devices ...
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Fig.18 and Fig. 19 show how to build a residue-voltage protection circuit /RESET Fig. 18 Circuit 1 for the Residue Voltage Protection ...
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Execute within two instruction cycles the "JMP", "CALL", "RET", "RETL", "RETI" commands, or the conditional skip ("JBS", "JBC", "JZ", "JZA", "DJZ", "DJZA") which were tested to be true. The instructions that are written to the program counter, should also ...
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0 0010 01rr rrrr 02rr 0 0010 10rr rrrr 02rr 0 0010 11rr rrrr 02rr 0 0011 00rr rrrr 03rr 0 0011 01rr rrrr 03rr 0 0011 10rr rrrr 03rr 0 0011 11rr rrrr 03rr 0 0100 00rr rrrr 04rr ...
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Timing Diagram AC Test Input/Output Waveform ...
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ABSOLUTE MAXIMUNM RATINGS Items Temperature under bias Storage temperature Input voltage Output voltage This specification is subject to change without prior notice. Rating - 150 C -0.3V to +6.0V -0.3V to +6.0V ...
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ELECTRICAL CHARACTERISTIC 6.1 DC ELECTRICAL CHARACTERISTIC ( Ta VDD= 5.0V 5%, VSS Symbol Parameter XTAL: VDD to 3V FXT XTAL: VDD to 5V ERC ERC: VDD to 5V IIL Input Leakage Current ...
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AC Electrical Characteristic (Ta VDD=5V 5%, VSS=0V) Symbol Parameter Dclk Input CLK duty cycle Instruction cycle time Tins (CLK="0") Ttcc TCC input period Tdrh Device reset hold time Trst /RESET pulse width Twdt Watchdog timer ...
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... Appendix Package Types: OTP MCU EM78P153EP EM78P153EN This specification is subject to change without prior notice. Package Type Pin Count DIP SOP 38 EM78P153E OTP ROM Package Size 14 300 mil 14 150 mil 2002/03/01 ...