MX29LV065TC-12 MCNIX [Macronix International], MX29LV065TC-12 Datasheet - Page 13

• Manufacturer Part Number: MX29LV065TC-12
• Description: 64M-BIT [8M x 8] CMOS EQUAL SECTOR FLASH MEMORY
• Manufacturer: MCNIX [Macronix International]

REQUIREMENTS FOR READING ARRAY
DATA
To read array data from the outputs, the system must
drive the CE and OE pins to VIL. CE is the power control
and selects the device. OE is the output control and gates
array data to the output pins. WE should remain at VIH.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory content
occurs during the power transition. No command is
necessary in this mode to obtain array data. Standard
microprocessor read cycles that assert valid address on
the device address inputs produce valid data on the device
data outputs. The device remains enabled for read access
until the command register contents are altered.
WRITE COMMANDS/COMMAND SEQUENCES
To program data to the device or erase sectors of memory
, the system must drive WE and CE to VIL, and OE to
VIH.
An erase operation can erase one sector, multiple sectors
, or the entire device. Table indicates the address space
that each sector occupies. A "sector address" consists
of the address bits required to uniquely select a sector.
The "Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 1 defines the valid register command
sequences. Writing incorrect address and data values or
writing them in the improper sequence resets the device
to reading array data". Section has details on erasing a
sector or the entire chip, or suspending/resuming the erase
operation.
After the system writes the auto-select command
sequence, the device enters the auto-select mode. The
system can then read auto-select codes from the internal
register (which is separate from the memory array) on
Q7-Q0. Standard read cycle timings apply in this mode.
Refer to the Auto-select Mode and Auto-select Command
Sequence section for more information.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification
table and timing diagrams for write operations.
P/N:PM0893
13
STANDBY MODE
MX29LV065 can be set into Standby mode with two dif-
ferent approaches. One is using both CE and RESET
pins and the other one is using RESET pin only.
When using both pins of CE and RESET, a CMOS
Standby mode is achieved with both pins held at Vcc ±
0.3V. Under this condition, the current consumed is less
than 0.2uA (typ.). If both of the CE and RESET are held
at VIH, but not within the range of VCC ± 0.3V, the device
will still be in the standby mode, but the standby current
will be larger. During Auto Algorithm operation, Vcc ac-
tive current (Icc2) is required even CE = "H" until the
operation is completed. The device can be read with stan-
dard access time (tCE) from either of these standby
modes.
When using only RESET, a CMOS standby mode is
achieved with RESET input held at Vss ± 0.3V, Under
this condition the current is consumed less than 1uA
(typ.). Once the RESET pin is taken high, the device is
back to active without recovery delay.
In the standby mode the outputs are in the high imped-
ance state, independent of the OE input.
MX29LV065 is capable to provide the Automatic Standby
Mode to restrain power consumption during read-out of
data. This mode can be used effectively with an applica-
tion requested low power consumption such as handy
terminals.
To active this mode, MX29LV065 automatically switch
themselves to low power mode when MX29LV065 ad-
dresses remain stable during access time of tACC+30ns.
It is not necessary to control CE, WE, and OE on the
mode. Under the mode, the current consumed is typi-
cally 0.2uA (CMOS level).
AUTOMATIC SLEEP MODE
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables this
mode when address remain stable for tACC+30ns. The
automatic sleep mode is independent of the CE, WE,
and OE control signals. Standard address access tim-
ings provide new data when addresses are changed. While
in sleep mode, output data is latched and always avail-
able to the system. ICC4 in the DC Characteristics table
represents the automatic sleep mode current specifica-
tion.
MX29LV065
REV. 0.4, JUL. 22, 2003