M12L16161A-4.3T ETC, M12L16161A-4.3T Datasheet - Page 5

• Manufacturer Part Number: M12L16161A-4.3T
• Description: 512K x 16Bit x 2Banks Synchronous DRAM
• Manufacturer: ETC

AC OPERATING TEST CONDITIONS
OPERATING AC PARAMETER
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
Elite Semiconductor Memory Technology Inc.
(AC operating conditions unless otherwise noted)
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
Row precharge time
Row active time
Row cycle time
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
Col. Address to col. Address delay
Number of valid output data
RAS to CAS delay
Output
4. Minimum delay is required to complete write.
4. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
870
and then rounding off to the next higher integer.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
è
(Fig.1) DC Output Load circuit
Parameter
Parameter
3.3V
1200
30 pF
è
CAS latency=3
CAS latency=2
Symbol
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
t
t
t
t
t
t
t
t
t
t
RRD
RCD
RP
RAS
RAS
RC
CDL
RDL
BDL
CCD
(min)
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(V
12.9
12.9
34.4
47.3
-4.3
8.6
DD
=3.3V 0.3V,T
P.5
10
15
15
40
55
tr / tf = 1 / 1
-5
See Fig.2
2.4 / 0.4
Value
1.4
1.4
-5.5
Output
16
16
40
60
11
Version
100
1
1
1
1
1
1
A
12
16
18
42
60
-6
= 0 to 70 C )
(Fig.2) AC Output Load Circuit
Publication Date : Jan. 2000
14
16
20
42
63
-7
Z0=50
16
20
20
48
68
-8
è
M12L16161A
CLK
CLK
CLK
CLK
Unit
ns
ns
ns
ns
us
ns
ea
Revision : 1.3u
Unit
ns
V
V
V
Vtt =1.4V
50
30 pF
è
Note
1
1
1
1
1
2
2
2
3
4