HD66108T00 HITACHI [Hitachi Semiconductor], HD66108T00 Datasheet
HD66108T00
Related parts for HD66108T00
HD66108T00 Summary of contents
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LCD Driver for Liquid Crystal Dot Description The HD66108T under control of an 8-bit MPU can drive a dot matrix graphic LCD (liquid-crystal display) employing bit-mapped display with support of an 8-bit MPU. Use of the HD66108T enables ...
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... LCD driving voltage: 6.0V to 15.0V Low current consumption: 400 µA max (at fOSC = 500 kHz, fOSC is external clock frequency) Package: 208-pin TCP (Tape-Carrier-Package) Ordering Information Type No. Package HD66108T00 208 pin TCP HD66108TA0 HD66108TB0 HCD66108BP Note: The details of TCP pattern are shown in “The Information of TCP.” ...
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HD66108 HD66108 Pad Location Coordinates Coordinate Pin Pad Pin Pad No. Name X Y No. Name (DMY23) 4040 –2550 34 X33 1 X0 –2450 35 X34 2 X1 –2350 36 X35 3 X2 –2250 37 X36 4 X3 –2150 38 ...
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Coordinate Pin Pad Pin No. Name X Y No. 134 X133 –4040 650 * 135 X134 550 * 136 X135 450 * 137 X136 350 * 138 X137 250 * 139 X138 150 * 140 X139 50 * 141 X140 ...
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... HD66108 Pin Arrangement X116 92 X152 56 Note : These figures of TCP are not drawn to a scale. 958 HD66108T00 (Top View) HD66108TA0 HD66108TB0 (Top View) 160 X48 196 X12 ...
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Pin Description Classification No. of Pins Symbol Power –V CC1 supply GND1–GND3 EE1 2, 7 V6L, V1L, 37, 42 V1R, V6R V4, V3, 6, 39, ...
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HD66108 No.of Classification Pins Symbol Control 10 OSC1 signals 11 OSC2 15, 16 TEST1, TEST2 960 No.of I/O Pins Function I 1 Input system clock pulses via this pin This pin outputs clock ...
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Internal Block Diagram VML1 VMH1 V V6L V4 V3 V1L V EE1 CC1 V –V CC2 CC3 GND1–GND3 M CL1 FLM M/S RESET CO OSC2 OSC1 TEST1 TEST2 X0 X31 X32 X99 X100 X164 V V1R VMH2 VHL2 CC4 Row/column ...
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HD66108 Register List Reg. No. Reg. Register Read Symbol Name Write 7 1 — — — — — Invalid — — — — AR Address DRAM ...
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System Description The HD66108T can assign a maximum of 65 out of 165 channels to row outputs for LCD driving. It also incorporates a timing generator and display memory, which are necessary to drive an LCD. If connected to an ...
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HD66108 Control bus MPU Data bus Figure 2 Basic System Configuration (2) 964 65-row 265 65-dot LCD output 165-column 100-column output output HD66108T HD66108T (Master chip) (Slave chip) LCD expansion signals LCD driving power supply ...
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Functional Description 1. Display Size Programming A variety of display sizes can be programmed by changing the system configuration and internal register settings. (1) System Configuration Using One HD66108T Chip When the 65-row-output mode is selected by internal register settings, ...
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HD66108 X: 100 dots (a) Configuration Using One HD66108T Chip (1) (65-Row Output from the Right Side) (c) Configuration Using One HD66108T Chip and One HD61203 as Row Driver (165-Column Output) Area displayed by (d) Configuration Using Two HD66108T Chips ...
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Display Memory Construction and Word Length Setting The HD66108T has a bit-mapped display memory of 165 MPU is stored in the display memory, with the MSB (most significant bit) on the left and the LSB (least significant bit) on ...
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HD66108 (H'00) 0(H'00) 1(H'01) 8 bit 63(H'3F) 64(H'40) Y address (a) Address Assignment When 1 Word Is 8 Bits Long (H'00) 0 0(H'00) 1(H'01) 6 bit 63(H'3F) 64(H'40) Y address (b) Address Assignment When 1 Word Is 6 Bits Long ...
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Display Data Write 3.1 Display Memory and Data Register Accesses (1) Access Figure 6 shows the relationship between the address register (AR) and internal registers and display memory in the HD66108T. Display memory shall be referred ...
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HD66108 (2) Busy Check A busy time period appears after display memory read/write address register write, since post-access processing is performed synchronously with internal clock pulses. Updating data in registers other than the address register is ...
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Dummy Read When reading out display data, the data which is read out immediately after setting the X and Y addresses is invalid. Valid data can be read out after one dummy read, which is performed after setting the ...
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HD66108 (4) Limitations on Access As shown in Figure 9, the display memory must not be rewritten until a time period of t has elapsed after rewriting the control register’s DUTY bits or the mode register’s FFS bits. However, display ...
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X address counted 0 Set address 1 Write display data 2 Reset X address 20 21 Dummy read/write 31 (1) Example of X Address Counter Increment (Word Length: 8 Bits) Y address counted 0 Set address 1 Write display data ...
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HD66108 4. Selection for LCD Driving Circuit Configuration 4.1 Row Output Pin Selection The HD66108T can assign a maximum of 65 pins for row outputs among the 165 pins named X0–X164. The X0–X164 pins can be classified into four blocks ...
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X32 X99 X0 X31 Column driver Column driver Block A Block B (a) LCD Driving Circuit Configuration Row driver 165-column output HD66108T (b) System Configuration Figure 11 165-Column-Output Mode X132 X164 X100 X131 Column driver Column driver Block C Block ...
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HD66108 X32 X0 X31 Column driver Block A Figure 12 65-Row-Output Mode from the Right Side 976 X99 X132 X100 X131 Column driver Row driver Block B Block C (a) LCD Driving Circuit Configuration 65-row LCD output 100-column output HD66108T ...
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X32 X99 X0 X31 Row driver Column driver Block A Block B (a) LCD Driving Circuit Configuration 32-row output LCD 100-column output HD66108T (b) System Configuration Figure 13 65-Row-Output Mode from the Left and Right Sides X132 X164 X100 X131 ...
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HD66108 X32 X0 X31 Column driver Block A Figure 14 33-Row-Output-Mode from the Right Side 978 X99 X132 X100 X131 Column driver Column driver Block B Block C (a) LCD Driving Circuit Configuration 33-row LCD output 132-column output HD66108T (b) ...
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Row Output Data Setting If certain LCD driving output pins are assigned to row output, data must be written to display memory for row output. The specific area to which this data must be written depends on the row-output ...
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HD66108 Control register ROS bit = 00 DUTY bit = 101 LCD driving voltages: VMH1 = V3, VML1 = V4, VMH2 = V3, VML2 = V4, VMH3 = V3, VML3 = V4 X0 --- Column driver Block A (32 bits) ...
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Control register ROS bit = 01 DUTY bit = 110 LCD driving voltages: VMH1 = V3, VML1 = V4, VMH2 = V2, VML2 = V5, VMH3 = V2, VML3 = V5 X0 --- --- X31 X32 --- Column driver Column ...
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HD66108 Control register ROS bit = 10 DUTY bit = 110 LCD driving voltages: VMH1 = V2, VML1 = V5, VMH2 = V3, VML2 = V4, VMH3 = V2, VML3 = V5 X0 --- Row driver Block A (32 bits) ...
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Control register ROS bit = 11 DUTY bit = 001 LCD driving voltages: VMH1 = V3, VML1 = V4, VMH2 = V3, VML2 = V4, VMH3 = V2, VML3 = V5 X0 --- --- X31 X32 --- Column driver Column ...
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HD66108 Control register ROS bit = 01 DUTY bit = 011 LCD driving voltages: VMH1 = V3, VML1 = V4, VMH2 = V2, VML2 = V5, VMH3 = V2, VML3 = V5 X0 --- Column driver Block A (32 bits) ...
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LCD Driving Voltage Setting There are 6 levels of LCD driving voltages ranging from the highest and V6 is the lowest. As shown in Figure 20, column output waveform is made ...
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HD66108 Row Column Column- row (non selected waveform) Column- row (selected waveform) Figure ...
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Multiplexing Duty Ratio and LCD Driving Waveform Settings A multiplexing duty ratio and LCD driving waveform can be selected via internal registers. A multiplexing duty ratio of 1/32, 1/34, 1/36, 1/48, 1/50, 1/64, or 1/66 can be selected according ...
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HD66108 Figure 22 LCD Driving Waveforms (Row Output with a 1/32 Multiplexing Duty Ratio) 988 ...
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Clock and Frame Frequency An input clock with a 200-kHz to 4-MH frequency can be used for the HD66108T. Note that raising clock frequency increases current consumption although it reduces busy time and enables high-speed operations. An optimum system ...
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HD66108 8. Standby Function The HD66108T has a standby function providing low-power dissipation. Writing bit 6 of the address register starts up the standby function. The LCD driving voltages, ranking from V1 to V6, must be set ...
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Table 4 Standby Status of Pins Pin Status OSC2 High CO Low CL1 Low (master chip) or high-impedance (slave chip) FLM Low (master chip) or high-impedance (slave chip) M Low (master chip) or high-impedance (slave chip (column output ...
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HD66108 Start-up Termination Notes: 1. Not necessary in the case of using internal oscillation. 2. Refer to equation 1 (Section 3.1). Figure 23 Start-Up and Termination of Standby Function and Related Operations 992 Set the LCD driving voltages to V ...
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Multi-Chip Operation Using multiple HD66108T chips (= multi-chip operation) provides the means for extending the number of display dots. Note the following items when using the multi-chip operation. (1) The master chip and the slave chips must be determined; ...
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HD66108 OSC1 FLM CL1 Note: Clock pulses for the slave chip can be supplied from the master chip's CO pin. Figure 24 Configuration Using Two HD66108T Chips (1) 994 LCD Column Column output output HD66108T HD66108T Slave mode Master mode ...
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LCD Column output HD66108T Master mode M OSC1 FLM CL1 Clock Note: Clock pulses for the slave chip can be supplied from the master chip CO pin. Figure 25 Configuration Using Two HD66108T Chips (2) HD66108 Row output Column output ...
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HD66108 HD61203U Row driver CR FRM CL2 Clock Notes: 1. The slave chip can oscillate CR clock pulses. In this case, the clock pulses must be supplied to the HD61203U from the HD66108T’s CO pin. 2. The HD61203U’s control pins ...
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Internal Registers All HD66108T’s registers can be read from and written into. However, the BUSY FLAG and invalid bits cannot be written to and reading invalid bits or registers returns 0’s. 1. Address Register (AR) (Accessed with ...
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HD66108 2. Display Memory (DRAM) (Accessed with Register Number = (B’000) Although display memory (Figure 28) is not a register, it can be handled as one 6-bit data can be selected by the control register ...
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Control Register (FCR) (Accessed with Register Number = (B’011) This register (Figure 31), containing eight bits, has a variety of functions such as specifying the method for accessing RAM, determining RAM valid area, and selecting the ...
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HD66108 6. Mode Register (MDR) (Accessed with Register Number = (B’100) This register (Figure 32), containing 3 invalid bits (D7 to D5) and 5 valid bits (D4 to D0), selects a system clock and type of LCD ...
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C Select Register (CSR) (Accessed with Register Number = (B’101) This register (Figure 33) contains 2 invalid bits (D7 and D6) and 5 valid bits (D5 to D0). It controls C- type waveforms and is activated ...
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HD66108 Reset Function The pin starts the HD66108T after power-on. A least 20 µs to prevent system failure due to excessive current created after power-on. Figure 34 shows the reset definition. (1) The Status of Pins during Reset Table 7 ...
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The Status of Registers during Reset The signal has no effect on registers or register bits except for the address register’s STBY bit and the X and Y address registers, which are reset to 0’s by the signal. Table ...
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HD66108 Precautionary Notes When Using the HD66108T (1) Install a 0.1-µF bypass capacitor as close to the LSI as possible to reduce power supply impedance (V –GND and V – (2) Do not leave input pins ...
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Absolute Maximum Ratings Item Symbol Power supply voltage (1) V CC1 Power supply voltage ( Input voltage Vin Operating temperature T op Storage temperature T stg Notes: 1. Permanent LSI damage may occur if the maximum ratings are ...
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HD66108 Electrical Characteristics DC Characteristics ( ±20%, GND = 0V unless otherwise noted) Item Symbol Min Input high OSC1 V voltage /S, CL1, FLM TEST1, TEST2 V The other inputs V Input low ...
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Item Symbol ON resistance X0–X164 R between Vi and Xj V pins voltage range ÆV Oscillating frequency f Notes: 1. When voltage applied to input pins is fixed to V capacity. 2. When the LSI is not exposed to light ...
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HD66108 DC Characteristics ( 2.7 to 4.0V, GND = 0V unless otherwise noted) Item Symbol Min Input high V voltage The other inputs V Input low S, OSC1, V voltage CL1, FLM, TEST1, TEST2, M The ...
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Figure 36 Driver Output Waveform and Voltage Levels HD66108 V V1, V2, V3 levels V V4, V5, V6 levels 1009 ...
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HD66108 AC Characteristics ( 4.5 to 6.0V, GND = 0V –20 to +75°C, unless otherwise noted CPU Bus Timing (Figure 37) Item high-level pulse width low-level pulse width high-level pulse width low-level pulse width ...
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AC Characteristics ( 2.7 to 4.5V, GND = 0V –20 to +75°C, unless otherwise noted CPU Bus Timing (Figure 37) Item high-level pulse width low-level pulse width high-level pulse width low-level pulse width – ...
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HD66108 DB0–DB7 CL1 FLM M Figure 38 LCD Interface Timing 1012 WWL WWH WWRH t ...
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All diodes are IS2074 130 pF Test Circuit Test Circuit 2 Figure 39 Load Circuits HD66108 H 1013 ...