HD66108T00 HITACHI [Hitachi Semiconductor], HD66108T00 Datasheet - Page 9

• Manufacturer Part Number: HD66108T00
• Description: (RAM-Provided 165-Channel LCD Driver for Liquid Crystal Dot Matrix Graphics)
• Manufacturer: HITACHI [Hitachi Semiconductor]

HD66108
Register List
CS RS 2 1 0 Symbol Name
1
0
0
0
0
0
0
0
0
0
Notes: 1. Shaded bits are invalid. Writing 1 or 0 to invalid bits does not affect LSI operation. Reading
962
— — — — —
0
1
1
1
1
1
1
1
1
Reg. No.
— — — AR
0 0 0 DRAM
0 0 1 XAR
0 1 0 YAR
0 1 1 FCR
1 0 0 MDR
1 0 1 CSR
1 1 0 —
1 1 1 —
2. DRAM is not actually a register but can be handled as one.
3. Setting the WLS bit of control register to 1 invalidates D7 and D6 bits of the display memory
4. DRAM must not be written to or read from until a time period of t
these bits returns 0.
register.
DUTY bit of FCR or the FFS bit of MDR. t
general, a time period of 1 ms or greater is sufficient if the frame frequency is 60–90 Hz.
D2 (duty correction value): 192 (duty = 1/32, 1/34, or 1/36)
Ni (frequency-division ratio specified by the mode register’s FFS bits):
f
CLK
t
: Input clock frequency (kHz)
CL1 =
Reg.
Ni·f
CLK
D2
(kHz)
Register Read/
Invalid
Address R
Display
memory
X
address
Y
address
Control
Mode
C select R
Invalid
Invalid
(ms) ................ Equation
Write 7
—
W
R
W
R
W
R
W
R
W
R
W
W
—
—
128 (duty = 1/48 or 1/50)
96 (duty = 1/64 or 1/66)
2, 1, 1/2, 1/3, 1/4, 1/6, or 1/8
Refer to “6. Clock and Frame Frequency.”
Busy STBY DISP
D7
INC
6
D6
WLS PON
5
D5
EOR
CL1
Data Bit Assignment
can be obtained from the following equation; in
4
D4
ROS
3
D3
YAD
FFS
2
D2
XAD
CLN
Register No.
DUTY
1
D1
CL1
DWS
has elapsed rewriting the
0
D0
Busy Time
—
None
8 clocks max
None
1.5 clocks max
None
1.5 clocks max
None
None
None
—
—
Notes
1
2
3