GM71C4403C-60 LG [LG Semicon Co.,Ltd.], GM71C4403C-60 Datasheet - Page 8

• Manufacturer Part Number: GM71C4403C-60
• Description: 1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
• Manufacturer: LG [LG Semicon Co.,Ltd.]

8
LG Semicon
Notes:
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t
sheet as electrical characteristics only if t
the data out pin will remain open circuit (high impedance) throughout the entire cycle if
t
modify-write and the data output will contain data read from the selected cell if neither of the
above sets of conditions is satisfied, the condition of the data out (at access time) is
indeterminate.
These parameters are referenced to CAS leading edge in early write cycles and to WE leading
edge in delayed write or a read modify write cycle.
t
Access time is determined by the longest among t
An initial pause of 100us is required after power up followed by a minimum of eight
initialization cycles (RAS only refresh cycle or CAS before RAS refresh cycle). If the internal
refresh counter is used, a minimum of eight CAS before RAS refresh cycles is required.
In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying
data to the device.
Test mode operation specified in this data sheet is 2bits test function controlled by control
address bit CA0. This test mode operation can be performed by WE-and-CAS-before-RAS
(WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read
cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the
condition of the output data is low level. In order to end this test mode operation, perform RAS
only refresh cycle or a CAS-before-RAS refresh cycle.
In a test mode read cycle, the value of t
the specified value. These parameters should be specified in test mode cycles by adding the
above value to the specified value in this data sheet.
AC measurements assume
Assumes that t
recommended value shown in this table, t
Measured with a lode circuit equivalent to 1 TTL loads and 100 pF.
Assumes that t
Assumes that t
t
open circuit condition and is not referenced to output voltage levels.
V
times are measured between V
Operation with the t
reference point only: if t
controlled exclusively by t
Operation with the t
reference point only: if t
controlled exclusively by t
WCS
RWD
RASP
OFF
IH
(min) and V
, t
(max),
>=t
defines RAS pulse width in extended data out mode cycles.
RWD
RWD
, t
(min), t
t
CWD,
OEZ(
RCD
RCD
RCD
max), t
IL
and t
(max) are reference levels for measuring timing of input signals.Also transition
>=t
<=t
<=t
CWD
RCD
RAD
AWD
RCD
RCD
t
RCD
>=t
T
OFR
= 2ns.
(max) limit insures that t
(max) limit insures that t
RCD
(max) and t
(max) and t
(max) and t
CWD
(max) and t
are not restrictive operating parameters. They are included in the data
RAD
CAC
AA
is greater than the specified t
.
(min), t
.
IH
is greater than the specified t
and V
RAD
RAD
AWD
RAD
WEZ
<=t
>=t
RAC
IL
<=t
>=t
(max) define the time at which the output achieves the
.
RAC
WCS
, t
RAD
RAD
RAD
AWD
AA
exceeds the value shown.
>=t
(max).
(max).
(max). If t
, t
(min) and t
CAC,
RAC
WCS
AA,
RAC
(max) can be met t
(max) can be met t
t
(min), the cycle is an early write cycle and
CAC
t
OAC
and t
RCD
RCD
and t
CPW
(max) limit, then access time is
or t
ACP
RAD
>=t
ACP
.
(max) limit, then access time is
RAD
CPW
is delayed for 2ns to 5ns for
(min), the cycle is a read-
is greater than the maximum
RCD
RAD
(max) is specified as a
(max) is specified as a
GM71C4403C