GM71C4403C-60 LG [LG Semicon Co.,Ltd.], GM71C4403C-60 Datasheet - Page 9
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GM71C4403C-60
Manufacturer Part Number
GM71C4403C-60
Description
1,048,576 WORDS x 4BIT CMOS DYNAMIC RAM
Manufacturer
LG [LG Semicon Co.,Ltd.]
Datasheet
1.GM71C4403C-60.pdf
(10 pages)
LG Semicon
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EDO Hi-Z control by OE or WE. OE rising edge disables data outputs. When OE goes high
during CAS high, the data will not come out until next CAS access. When WE goes low
during CAS high, the data will not come out until next CAS access.
t
cycles. If both write and read operation are mixed in a EDO mode RAS cycle(EDO mode
mix cycle (1),(2) ) minimum value of CAS cycle (t
specified t
EDO mode mix cycle (1) and (2).
Either t
t
t
t
t
HPC
RAS
CAS
OFF
CSH
(min) can be achieved during a series of EDO mode write cycles or EDO mode read
(min) = t
(min) = t
(min) can be achieved when t
and t
RCH
OFR
HPC
or t
RWD
CWD
are determined by the later rising edge of RAS or CAS.
(min) value.The value of CAS cycle time of mixed EDO mode is shown in
RRH
(min) + t
(min) + t
must be satisfied.
RWL
CWL
(min) + t
(min) + t
RCD
<= t
T
T
in Read - Modify - Write cycle.
in Read - Modify - Write cycle.
CSH
(min) - t
CAS
CAS
(min).
+ t
CP
+ 2t
T
) becomes greater than the
GM71C4403C
9