DM9000A_06 DAVICOM [Davicom Semiconductor, Inc.], DM9000A_06 Datasheet
DM9000A_06
Related parts for DM9000A_06
DM9000A_06 Summary of contents
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DAVICOM Semiconductor, Inc. with General Processor Interface Final Version: DM9000A-17-DS-F01 May 10, 2006 Ethernet Controller with General Processor Interface DM9000A Ethernet Controller DATA SHEET DM9000A Final Version : DM9000A-DS-F01 May 10, 2006 1 ...
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General Description............................................................................................................................................................ 6 2. Block Diagram .................................................................................................................................................................... 6 3. Features ............................................................................................................................................................................... 7 4. Pin Configuration ............................................................................................................................................................... 8 4.1 (16-bit mode) ................................................................................................................................................................. 8 4.2 (8-bit mode) ................................................................................................................................................................... 9 5. Pin Description.................................................................................................................................................................. 10 5.1 Processor Interface ...................................................................................................................................................... 10 5.1.1 8-bit mode ...
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Wake Up Control Register ( 0FH ) (in 8-bit mode).................................................................................................... 20 6.16 Physical Address Register ( 10H~15H ) .................................................................................................................... 20 6.17 Multicast Address Register ( 16H~1DH ) .................................................................................................................. 20 6.18 General purpose control Register ( 1EH ) ( For ...
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Basic Mode Control Register (BMCR ................................................................................................................. 30 8.2 Basic Mode Status Register (BMSR) - 01..................................................................................................................... 31 8.3 PHY ID Identifier Register #1 (PHYID1 ............................................................................................................. 33 8.4 PHY ID Identifier Register #2 (PHYID2 ............................................................................................................. ...
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Reduced Transmit Power Mode ......................................................................................................................... 47 10. DC and AC Electrical Characteristics .......................................................................................................................... 48 10.1 Absolute Maximum Ratings ( 25 10.1.1 Operating Conditions ......................................................................................................................................... 48 10.2 DC Electrical Characteristics (VDD = 3.3V)............................................................................................................ 48 10.3 AC Electrical Characteristics & Timing ...
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General Description The DM9000A is a fully integrated and cost-effective low pin count single chip Fast Ethernet controller with a general processor interface, a 10/100M PHY and 4K Dword SRAM designed with low power and high performance ...
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Features ■ 48-pin LQFP ■ Supports processor interface: byte/word of I/O command to internal memory data operation ■ Integrated 10/100M transceiver with HP Auto-MDIX ■ Supports back pressure mode for half-duplex mode flow control ■ IEEE802.3x flow control for ...
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Pin Configuration 4.1 (16-bit mode) CS# LED2 LED1 PWRST# TEST VDD X2 X1 GND SD RXGND BGGND Final Version: DM9000A-17-DS-F01 May 10, 2006 Ethernet Controller with General Processor Interface DM9000A 42 (16-bit mode) 43 ...
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CS# LED2 LED1 PWRST# TEST VDD X2 X1 GND SD RXGND BGGND Final Version: DM9000A-17-DS-F01 May 10, 2006 Ethernet Controller with General Processor Interface DM9000A 42 (8-bit mode ...
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Pin Description I = Input O = Output # = asserted low 5.1 Processor Interface Pin No. Pin Name 35 IOR# 36 IOW# 37 CS# 32 CMD 34 INT O,PD 18,17,16, 14,13,12, SD0~7 I/O,PD 11,10 31,29,28, 27,26,25, SD8~15 I/O,PD ...
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EEPROM Interface Pin No. Pin Name I/O,PD IO Data to EEPROM 19 EEDIO 20 EECK O,PD 21 EECS O,PD 5.3 Clock Interface Pin No. Pin Name 5.4 LED Interface Pin No. Pin Name 39 LED1 ...
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RX- 5,47 RXGND 6 TXGND 7 TX+ 8 TX- 5.6 Miscellaneous Pin No. Pin Name 41 TEST 40 PWRST# 5.7 Power Pins Pin No. Pin Name 23,30,42 VDD 15,33,45 GND 5.8 strap pins table 1: pull-high 1K~10K, 0: floating ...
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Vendor Control and Status Register Set The DM9000A implements several control and status registers, which can be accessed by the host. These CSRs Register NCR Network Control Register NSR Network Status Register TCR TX Control Register TSR I TX ...
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RSCCR Resume System Clock Control Register MRCMDX Memory Data Pre-Fetch Read Command Without Address Increment Register MRCMDX1 Memory Data Read Command With Address Increment Register MRCMD Memory Data Read Command With Address Increment Register MRRL Memory Data Read_ address Register ...
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Network Status Register (01H) Bit Name Default 7 SPEED X,RO 6 LINKST X,RO P0, 5 WAKEST RW/C1 4 RESERVED 0,RO PS0, 3 TX2END RW/C1 PS0, 2 TX1END RW/C1 1 RXOV PS0,RO 0 RESERVED 0,RO 6.3 TX Control Register (02H) ...
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RESERVED 0,RO 6.5 TX Status Register II ( 04H ) for packet index I I Bit Name Default 7 TJTO PS0, PS0, PS0, PS0,RO 3 COL PS0, PS0,RO 1:0 RESERVED 0,RO ...
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CE PS0,RO 0 FOE PS0,RO 6.8 Receive Overflow Counter Register ( 07H ) Bit Name Default 7 RXFU PS0,R/C 6:0 ROC PS0,R/C 6.9 Back Pressure Threshold Register (08H) Bit Name Default 7:4 BPHW PS3, RW 3:0 JPT PS7, RW ...
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LWOT PS8, RW Final Version: DM9000A-17-DS-F01 May 10, 2006 Ethernet Controller with General Processor Interface RX FIFO Low Water Overflow Threshold Send a pause packet with pause_time=0000 when RX SRAM free space is larger than this value. This pause ...
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RX/TX Flow Control Register ( 0AH ) Bit Name Default 7 TXP0 PS0,RW 6 TXPF PS0,RW 5 TXPEN PS0,RW 4 BKPA PS0,RW 3 BKPM PS0,RW 2 RXPS PS0,R/C 1 RXPCS PS0,RO 0 FLCE PS0,RW 6.12 EEPROM & PHY Control ...
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Wake Up Control Register ( 0FH ) (in 8-bit mode) Bit Name Type 7:6 RESERVED 0,RO 5 LINKEN P0,RW 4 SAMPLEEN P0,RW 3 MAGICEN P0,RW 2 LINKST P0,RO 1 SAMPLEST P0,RO 0 MAGICST P0,RO 6.16 Physical Address Register ( ...
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P, 3:1 GPC31 000,RW 0 RESERVED P1,RO Final Version: DM9000A-17-DS-F01 May 10, 2006 Ethernet Controller with General Processor Interface General Purpose Control 3~1 Define the input/output direction of pins GP 3~1 respectively. When a bit is set 1, the direction ...
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General purpose Register ( 1FH ) ( For 8 Bit mode only, For 16 bit mode, see reg . 34H) Bit Name Default 7 RESERVED 0,RO 6-4 GPO P0,RW P0,RW 3:1 GPIO 0 PHYPD ET1,WO 6.20 TX SRAM Read ...
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DTU P0,RW 4 ONEPM P0,RW 3~0 IFGS P0,RW 6.26 Operation Test Control Register ( 2EH ) Bit Name Default 7~6 SCC P0,RW 5 RESERVED P0,RW 4 SOE P0,RW 3 SCS P0,RW 2~0 PHYOP P0,RW 6.27 Special Mode Control Register ...
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Early Transmit Control/Status Register ( 30H ) Bit Name Default 7 ETE PS0 ETS2 PS0,RO 5 ETS1 PS0,RO 4~2 RESERVED 000,RO 1~0 ETT PS0,RW 6.29 Check Sum Control Register ( 31H ) Bit Name Default 7~3 RESERVED ...
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MII PHY Address Register ( 33H ) Bit Name Default 7 ADR_EN HPS0,R W 6~5 Reserved HPS0,RO Reserved 4~0 EPHYADR HPS01,R W 6.32 LED Pin Control Register ( 34H ) Bit Name Default 7:2 Reserved PS0,RO 1 GPIO P0,RW ...
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INT Pin Control Register ( 39H ) Bit Name Default 7:2 Reserved PS0,RO 1 INT_TYPE PET0,RW 0 INT_POL PET0,RW 6.35 System Clock Turn ON Control Register ( 50H ) Bit Name Default 7:1 Reserved - 0 DIS_CLK P0,W 6.36 ...
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MWCMDX X,WO 6.42 Memory data write command with address increment Register (F8H) Bit Name Default 7:0 MWCMD X,WO 6.43 Memory data write_address Register (FAH~FBH) Bit Name Default 7:0 MDWAH PS0,RW 7:0 MDWAL PS0,RW 6.44 TX Packet Length Register (FCH~FDH) ...
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EEPROM Format name Word MAC address 0 Auto Load Control 3 Vendor ID 4 Product ID 5 pin control 6 Wake-up mode control 7 Final Version: DM9000A-17-DS-F01 May 10, 2006 Ethernet Controller with General Processor Interface offset 0~5 6 ...
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PHY Register Description ADD Name CONTR Reset Loop Speed Auto-N OL back select Enable STATUS T4 TX FDX TX HDX 10 FDX Cap. Cap. Cap. Cap ...
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Basic Mode Control Register (BMCR Bit Bit Name 0.15 Reset 0.14 Loopback 0.13 Speed selection 0.12 Auto-negotiatio n enable 0.11 Power down 0.10 Isolate 0.9 Restart Auto-negotiation Final Version: DM9000A-17-DS-F01 May 10, 2006 Ethernet Controller with General ...
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Duplex mode 0.7 Collision test 0.6-0.0 Reserved 8.2 Basic Mode Status Register (BMSR Bit Bit Name 1.15 100BASE-T4 1.14 100BASE-TX full-duplex 1.13 100BASE-TX half-duplex 1.12 10BASE-T full-duplex 1.11 10BASE-T half-duplex 1.10-1.7 Reserved 1.6 MF preamble Final Version: ...
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Auto-negotiation Complete 1.4 Remote fault Auto-negotiation 1.3 ability 1.2 Link status 1.1 Jabber detect 1.0 Extended capability Final Version: DM9000A-17-DS-F01 May 10, 2006 Ethernet Controller with General Processor Interface 1 = PHY will accept management frames with preamble ...
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PHY ID Identifier Register #1 (PHYID1 The PHY Identifier Registers #1 and #2 work together in a single identifier of the DM9000A. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), a vendor's model ...
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Auto-negotiation Advertisement Register (ANAR This register contains the advertised abilities of this DM9000A device as they will be transmitted to its link partner during Auto-negotiation. Bit Bit Name 4.15 NP 4.14 ACK 4.13 RF 4.12 Reserved -4.11 ...
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Selector 8.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 05 This register contains the advertised abilities of the link partner when received during Auto-negotiation. Bit Bit Name 5.15 NP 5.14 ACK 5.13 RF 5.12 Reserved -5.11 5.10 FCS 5.9 ...
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Selector 8.7 Auto-negotiation Expansion Register (ANER)- 06 Bit Bit Name 6.15-6.5 Reserved 6.4 PDF 6.3 LP_NP_ABL E 6.2 NP_ABLE 6.1 PAGE_RX 6.0 LP_AN_ABL E 8.8 DAVICOM Specified Configuration Register (DSCR Bit Bit Name ...
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BP_ALIGN 16.12 BP_ADPOK 16.11 Reserved 16.10 TX/FX 16.9 Reserved 16.8 Reserved 16.7 F_LINK_100 16.6 SPLED_CTL 16.5 COLLED_CT L 16.4 RPDCTR-EN 16.3 SMRST 16.2 MFPSC 16.1 SLEEP Final Version: DM9000A-17-DS-F01 May 10, 2006 Ethernet Controller with General Processor Interface 1 ...
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RLOUT 8.9 DAVICOM Specified Configuration and Status Register (DSCSR Bit Bit Name Default 17.15 100FDX 1, RO 17.14 100HDX 1, RO 17.13 10FDX 1, RO 17.12 10HDX 1, RO 17.11 Reserved 0, RO -17.9 17.8 PHYADR (PHYADR), ...
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ANMB[ -17.0 0] 8.10 10BASE-T Configuration/Status (10BTCSR Bit Bit Name Default 18.15 Reserved 0, RO 18.14 LP_EN 1, RW 18.13 HBE 1,RW 18.12 SQUELCH 1, RW 18.11 JABEN 1, RW 18.10 Reserved 0, RW 18.9 ...
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POLR 0, RO 8.11 Power Down Control Register (PWDOR Bit Bit Name Default 19.15 Reserved 0, RO -19.9 19.8 PD10DRV 0, RW 19.7 PD100DL 0, RW 19.6 PDchip 0, RW 19.5 PDcom 0, RW 19.4 PDaeq 0, ...
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Mdix_down 20.3 MonSel1 20.2 MonSel0 20.1 Reserved 20.0 PD_value Final Version: DM9000A-17-DS-F01 May 10, 2006 Ethernet Controller with General Processor Interface 0,RW HP Auto-MDIX Down Manual force MDI/MDIX. 0: Enable HP Auto-MDIX 1: Disable HP Auto-MDIX , MDIX_CNTL value ...
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Functional Description 9.1 Host Interface The host interface is a general processor local bus that using chip select (pin CS#) to access DM9000A. Pin CS# is default low active which can be re-defined by EEPROM setting. There are only ...
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Operation The transmitter section contains the following functional blocks: - 4B5B Encoder - Scrambler - Parallel to Serial Converter - NRZ to NRZI Converter - NRZI to MLT-3 - MLT-3 Driver 9.5.1 4B5B Encoder The 4B5B encoder converts ...
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Code Group Symbol Final Version: DM9000A-17-DS-F01 ...
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Receiver The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to synchronous 4-bit nibble data. The receive section contains the following functional blocks: - Signal Detect - Digital Adaptive Equalization - MLT-3 to ...
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Code Group Alignment The Code Group Alignment block receives un-aligned 5B data from the descrambler and converts it into 5B code group data. Code Group Alignment occurs after the J/K is detected, and subsequent data is aligned on a ...
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Power Reduced Mode The Signal detect circuit is always turned to monitor whether there is any signal on the media (cable disconnected). The DM9000A automatically turns off the power and enters the Power Reduced mode, whether its operation mode ...
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DC and AC Electrical Characteristics 10.1 Absolute Maximum Ratings ( 25°C ) Symbol D Supply Voltage VDD V DC Input Voltage (VIN Output Voltage(VOUT) OUT Tstg Storage Temperature range Tc Case Temperature TA Ambient Temperature LT ...
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AC Electrical Characteristics & Timing Waveforms 10.3.1 TP Interface Symbol Parameter t 100TX+/- Differential Rise/Fall Time TR/F t 100TX+/- Differential Rise/Fall Time TM Mismatch t 100TX+/- Differential Output Duty Cycle TDC Distortion T 100TX+/- Differential Output Peak-to-Peak t/T Jitter ...
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Processor I/O Write Timing CS# , CMD IOW# SD IO16 Symbol T CS#,CMD valid to IOW# valid 1 T IOW# Width 2 T System Data(SD) Setup Time 3 T System Data(SD) Hold Time 4 T IOW# Invalid to CS#,CMD ...
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EEPROM Interface Timing EECS EECK EEDIO Symbol T EECK Frequency 1 T2 EECS Setup Time T EECS Hold Time 3 T EEDIO Setup Time when output 4 T5 EEDIO Hold Time when output T EEDIO Setup Time when input ...
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Application Notes 11.1 Network Interface Signal Routing Place the transformer as close as possible to the RJ-45 connector. Place all the 50Ω resistors as close as possible to the DM9000A RXI± and TXO± pins. Traces routed from RXI± and ...
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Non Auto MDIX Transformer Application ) 3 RXI+ 4 RXI- AVDD_25 2 AVDD_25 9 DM9000A 7 TX0+ 8 TX0- 1 BGRES 48 BGGND Final Version: DM9000A-17-DS-F01 May 10, 2006 Ethernet Controller with General Processor Interface Transformer 50 ...
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Power Decoupling Capacitors Davicom Semiconductor recommends placing all the decoupling capacitors for all power supply pins as close as possible to the power pads of the DM9000A (The best placed distance is < 3mm from pin). The recommended decoupling ...
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Ground Plane Layout Davicom Semiconductor recommends a single ground plane approach to minimize EMI. Ground plane partitioning can cause increased EMI emissions that could make the network interface card not comply with specific FCC Final Version: DM9000A-17-DS-F01 May 10, ...
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Power Plane Partitioning The power planes should be approximately illustrated in Figure 11-5. Final Version: DM9000A-17-DS-F01 May 10, 2006 Ethernet Controller with General Processor Interface Figure 11-5 Power Plane Partitioning DM9000A 56 ...
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Magnetics Selection Guide Refer to Table 2 for transformer requirements. Transformers, meeting these requirements, are available from a variety of magnetic manufacturers. Designers should test and qualify all magnetics before Manufacturer Pulse Engineering Delta YCL MAGCOM Halo Nano Pulse ...
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Package Information LQFP 48L (F.P. 2mm) Outline Dimensions Symbol Dimensions in inches Min. Nom. Max 0.063 A1 0.002 - 0.006 A2 0.053 0.055 0.057 b 0.007 0.009 0.011 b1 0.007 0.008 0.009 C 0.004 - 0.008 ...
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Ordering Information Part Number Pin Count DM9000AE 48 DM9000AEP 48 Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in ...
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Ethernet Controller with General Processor Interface Final Version: DM9000A-17-DS-F01 May 10, 2006 DM9000A 60 ...