DM9010BI DAVICOM [Davicom Semiconductor, Inc.], DM9010BI Datasheet
DM9010BI
Related parts for DM9010BI
DM9010BI Summary of contents
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... DAVICOM Semiconductor, Inc. Industrial-temperature 10/100 Mbps Single Chip With General Processor Interface Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface DM9010BI Ethernet Controller DATA SHEET DM9010BI Preliminary Version: DM9010BI-DS-P01 January 12, 2010 1 ...
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... C PERATION EST ONTROL 6. PECIAL ODE ONTROL 6. ARLY RANSMIT ONTROL Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Content MII I ................................................................................................................. 7 NTERFACE 32 ............................................................................................................. 8 IT ATA US (00H) .......................................................................................................................... 16 (01H).............................................................................................................................. 16 I..................................................................................................... 17 FOR PACKET INDEX I I ................................................................................................. 17 ...
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... Encoder ...................................................................................................................................................... 41 9.5.2 Scrambler ............................................................................................................................................................. 41 9.5.3 Parallel to Serial Converter................................................................................................................................. 41 9.5.4 NRZ to NRZI Encoder .......................................................................................................................................... 41 9.5.5 MLT-3 Converter.................................................................................................................................................. 41 9.5.6 MLT-3 Driver ....................................................................................................................................................... 41 9.5.7 4B5B Code Group ................................................................................................................................................ 42 9.6 100B -TX R ............................................................................................................................................... 43 ASE ECEIVER Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface R (31H).................................................................................................... 24 EGISTER S R (32H).......................................................................................... 24 TATUS EGISTER R (33H).................................................................................................... 24 ...
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... AGNETICS ELECTION 11 ............................................................................................................................................. 57 RYSTAL ELECTION UIDE 11.9 A MII.......................................................................................................................................... 58 PPLICATION OF REVERSE 12. PACKAGE INFORMATION ........................................................................................................................................ 59 13. ORDERING INFORMATION........................................................................................................................................... 60 Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface (-40°C ~ +85°C)....................................................................................................... 46 ......................................................................................................................................... 46 (VDD = 3.3V) ................................................................................................... 46 & ...................................................................................... 47 IMING AVEFORMS R .................................................................................................................... 52 OUTING -MDIX A ...
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... IEEE 802.3u Spec. Its auto-negotiation function will automatically configure the DM9010BI to take the maximum advantage of its abilities. The DM9010BI also supports IEEE 802.3x full- duplex flow control. This programming of the DM9010BI is very simple, so user can port the software drivers to any system easily. ...
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... Build in 3.3V to 1.8V regulator ■ Supports early Transmit ■ Supports IP/TCP/UDP checksum generation and checking Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface ■ Supports automatically load vendor ID and product ID from EEPROM ■ Supports GPIO pins ■ ...
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... SD9 89 SD8 90 VDD 91 IO16 92 CMD 93 SA4 94 SA5 95 SA6 96 SA7 97 SA8 98 SA9 99 GND 100 INT Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface DM9010BI DM9010BI 50 TXD0 49 TXC 48 TEST5 47 RXC 46 RXER 45 RXDV 44 COL 43 CRS 42 GND 41 RXD3 40 ...
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... SD9 89 SD8 90 VDD 91 IO16 92 CMD 93 SA4 94 SA5 95 SA6 96 SA7 97 SA8 98 SA9 99 GND 100 INT Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface DM9010BI DM9010BI 50 SD20 49 SD21 48 TEST5 47 SD22 46 SD23 45 SD24 44 SD25 43 SD26 42 GND 41 SD27 40 ...
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... This pin is low active at default; its polarity can be modified by EEPROM setting. See the EEPROM content description for detail I,PD Address Enable A low active signal used to select the DM9010BI. Processor Command Ready When a command is issued before last command is completed, the IOWAIT will be pulled low to indicate the current command is waited The polarity and output type can be updated by EEPROM ...
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... This pin is high active at default, its polarity can be modified by EEPROM setting or strap pin MDC. See the EEPROM content description for detail These pins are used as data bus bits 16~31 when the DM9010BI is set to double word mode (the straps pin EEDO is pulled high and WAKE is not ...
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... SPLED 61 FDLED 62 LKLED Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface I Data from EEPROM This pin is also used as a strap pin. It combines with strap pin WOL, and it can set the data width of the internal memory access ...
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... MII interface (pulled high normal MII interface (not pulled high). This pin has a pulled down resistor about 60k ohm internally. This pin has a pulled down resistor about 60k ohm internally. I Power on Reset Active low signal to initiate the DM9010BI The DM9010BI is ready after 5us when this pin deasserted NC NC DM9010BI 12 ...
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... Output Type of INT 1: INT pin is Open-Collect 0: INT pin is force output 77 GPIO6 HP Auto-MDIX 0: HP Auto-MDIX turn Auto-MDIX turn OFF Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface P Digital VDD P Digital GND EEDO data width ...
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... VENDOR CONTROL AND STATUS REGISTER SET The DM9010BI implements several control and status registers, which can be accessed by the host. These CSRs Register Description NCR Network Control Register NSR Network Status Register TCR TX Control Register TSR I TX Status Register I TSR II TX Status Register II ...
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... X No default value P = power on reset default value H = hardware reset default value S = software reset default value Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface E = default value from EEPROM T = default value from strap pin <Access Type>: ...
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... CRC_DIS1 PHS0,RW 0 TXREQ PHS0,RW Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Selects external PHY when set. Selects Internal PHY when clear. This bit will not be affected after software reset Wakeup Event Enable When set, it enables the wakeup function. Clearing this bit will also clears all ...
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... PRMSC PHS0,RW 0 RXEN PHS0,RW Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Transmit Jabber Time Out It is set to indicate that the transmitted frame is truncated due to more than 2048 bytes are transmitted Loss of Carrier It is set to indicate the loss of carrier during the frame transmission not valid in ...
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... RXFU PHS0,R/C 6:0 ROC PHS0,R/C Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Runt Frame It is set to indicate that the size of the received frame is smaller than 64 bytes Multicast Frame It is set to indicate that the received frame has a multicast address ...
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... HPS0,RW 5 TXPEN HPS0,RW Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Back Pressure High Water Overflow Threshold. MAC will generate the jam pattern when RX SRAM free space is lower than this threshold value Default is 3K-byte free space. Please do not exceed SRAM size (1 unit=1K bytes) Jam Pattern Time ...
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... SAMPLEEN P0,RW 3 MAGICEN P0,RW Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Back Pressure Mode This mode is for half duplex mode only. It generates a jam pattern when any packet comes and RX SRAM is over BPHW Back Pressure Mode This mode is for half duplex mode only. It generates a jam pattern when a packet’ ...
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... GEPIO6-4 PH0,RW Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface This bit will not be affected after software reset When set, it indicates that Link Change and Link Status Change Event occurred This bit will not be affected after software reset When set, it indicates that the sample frame is received and Sample Frame Event occurred ...
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... Name Default 7 LED PH0,RW Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface General Purpose 3~1 When the correspondent bit of General Purpose Control Register is 1, the value of the bit is reflected to pin GEPIO3-1 When the correspondent bit of General Purpose Control Register is 0, the value of ...
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... Bit Name Default 7 ETE HPS0, RW Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Retry Late Collision Packet Re-transmit the packet with late-collision Disable TX Under run Retry Disable to re-transmit the underruned packet One Packet Mode When set, only one packet transmit command can be issued before transmit completed ...
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... Reserved HPS0,RO Reserved 4~0 EPHYADR HPS01,R W Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Early Transmit Status II (under run) Early Transmit Status I (under run) Reserved Early Transmit Threshold Start transmit when data write to TX FIFO reach the byte-count threshold ...
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... IOW_SPIKE P0,RW 0 IOR_SPIKE P1,RW Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface General Purpose Control 2 Define the input/output direction of pins SD23~16, which are used as general purpose pins when none 32-bit mode and external MII mode, respectively. ...
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... PHYceiver also power down 0: internal system clock is ON Read data from RX SRAM. After the read of this command, the read pointer of internal SRAM is unchanged. And the DM9010BI starts to pre-fetch the SRAM data to internal data buffers. DM9010BI ...
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... PHS0,RW TX Packet Length High byte 7:0 TXPLL PHS0,RW TX Packet Length Low byte Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Read data from RX SRAM. After the read of this command, the read pointer of internal SRAM is unchanged. ...
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... UDRUNI PHS0,RW 3 ROOI PHS0,RW 2 ROI PHS0,RW 1 PTI PHS0,RW 0 PRI PHS0,RW Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Bit 7 Bit 16-bit mode 0 1 32-bit mode 1 0 8-bit mode 1 1 Reserved Link Status Change ...
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... Wake-up mode control 7 RESERVED 8 RESERVED 9 RESERVED 10 RESERVED 11 Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface offset 0~5 6 Byte Ethernet Address 6-7 Bit 1:0=01: Update vendor ID and product ID Bit 3:2=01: Accept setting of WORD6 [8:0] Bit 5:4=01: Accept setting of WORD6 [11:9] Bit 7:6=01: Accept setting of WORD7 [3:0] ...
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... Value>, <Access Type> / <Attribute(s)> Where： <Reset Value>: 1 Bit set to logic one 0 Bit set to logic zero X No default value Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Power Isolate Restart Full Coll ...
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... When auto-negotiation is disabled (bit 12 of this register cleared), this bit has no function and it should be cleared. This bit is self-clearing and it will keep returning to a value of 1 until auto-negotiation is initiated by the DM9010BI. The operation of the auto-negotiation process will not be affected by the management entity that clears this bit ...
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... DM9010BI is not able to perform 100BASE-TX in half duplex mode 1,RO/P 10BASE-T Full Duplex Capable 1 = DM9010BI is able to perform 10BASE-T in full duplex mode 0 = DM9010BI is not able to perform 10BASE-TX in full duplex mode 1,RO/P 10BASE-T Half Duplex Capable 1 = DM9010BI is able to perform 10BASE-T in half duplex mode 0 = DM9010BI is not able to perform 10BASE-T in half duplex mode ...
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... PHY ID Identifier Register #2 (PHYID2 Bit Bit Name 3.15-3.10 OUI_LSB 3.9-3.4 VNDR_MDL 3.3-3.0 MDL_REV 8.5 Auto-negotiation Advertisement Register (ANAR This register contains the advertised abilities of this DM9010BI device as they will be transmitted to its link partner during Auto-negotiation. Bit Bit Name 4.15 NP 4.14 ACK Preliminary Version: DM9010BI--DS-P01 January 12, 2010 ...
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... Controller chip doesn’t support flow control ability 0, RO/P 100BASE-T4 Support 1 = 100BASE-T4 is supported by the local device 0 = 100BASE-T4 is not supported The DM9010BI does not support 100BASE-T4 so this bit is permanently set 100BASE-TX Full Duplex Support 1 = 100BASE-TX full duplex is supported by the local device ...
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... Local Device Next Page Able NP_ABLE = 1: DM9010BI, next page available NP_ABLE = 0: DM9010BI, no next page DM9010BI does not support this function, so this bit is always 0 0, RO/LH New Page Received A new link code word page received. This bit will be automatically cleared when the register (register 6) is read by management ...
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... RPDCTR-EN 16.3 SMRST 16.2 MFPSC 16.1 SLEEP 16.0 RLOUT Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface 0 = Normal operation 0, RW BYPASS ADPOK Force signal detector (SD) active. This register is for debug only, not release to customer 1=Forced SD is OK, 0=Normal operation ...
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... RW :0] 17.3-17.0 ANMB[3: Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface 100M Full Duplex Operation Mode After auto-negotiation is completed, results will be written to this bit. If this bit means the operation 1 mode is a 100M full duplex mode. The software can read bit [15:12] to see which mode is selected after auto-negotiation ...
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... Link pulses disabled, good link condition forced This bit is valid only in 10Mbps operation Heartbeat Enable 1 = Heartbeat function enabled 0 = Heartbeat function disabled When the DM9010BI is configured for full duplex operation, this bit will be ignored (the collision/heartbeat function is invalid in full duplex mode) Squelch Enable 1 = Normal squelch ...
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... Mdix_fix Value 20.4 Mdix_down 20.3 MonSel1 20.2 MonSel0 20.1 Reserved 20.0 PD_value Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Default 0,RW Vendor test select control 0,RW Vendor test select control 0,RW Force Signal Detect 1: force SD signal OK in 100M 0: normal SD signal. 0,RW Vendor test select control ...
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... DMA port and then write the byte count to byte_ count register at index register 0fch and 0fdh. Set the bit 1 of control register. The DM9010BI starts to transmit the index I packet. Before the transmission of the index I packet ends, the data of the next (index II) packet can be moved to TX SRAM ...
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... IDLEs into the transmit data stream until Transmit Enable is asserted and the next transmit packet is detected. The DM9010BI includes a Bypass 4B5B conversion option within the 100Base-TX Transmitter for support of applications like 100 Mbps repeaters which do not require 4B5B conversion. ...
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... Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Meaning 4B code 3210 Data 0 0000 Data 1 0001 Data 2 0010 Data 3 0011 Data 4 0100 Data 5 0101 Data 6 0110 ...
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... Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface 9.6.3 MLT-3 to NRZI Decoder The DM9010BI decodes the MLT-3 information from the Digital Adaptive Equalizer into NRZI data. The relationship between NRZI and MLT-3 data is shown In figure 4. 9.6.4 Clock Recovery Module The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder ...
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... The T/R symbol pair is also stripped from the nibble, presented to the Reconciliation layer. 9.7 10Base-T Operation The 10Base-T transceiver is IEEE 802.3u compliant. When the DM9010BI is operating in 10Base-T mode, the coding scheme is Manchester. Data processed for transmit is presented to the MII interface in nibble format, converted to a serial bit stream, then the Manchester encoded ...
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... Power Reduced Mode The Signal detect circuit is always turned to monitor whether there is any signal on the media (cable disconnected). The DM9010BI automatically turns off the power and enters the Power Reduced mode, whether its operation mode is N-way or force mode. When enters the Power Reduced mode, the transmit circuit still sends out fast link pules with minimum power consumption ...
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... Differential Output TD100 Voltage V 10TX+/- Differential Output Voltage TD10 I 100TX+/- Differential Output TD100 Current I 10TX+/- Differential Output Current TD10 Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Parameter Min. -0.3 -0.5 -0.3 -65 -40 - Min. 3.135 --- ...
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... T4 PWRST# high to EECS burst end Note: The DM9010BI needs the time about 3ms to down load the setting from EEPROM after PWRST# deasserted, During the period, the processor command (IOR#, IOW#, AEN#) pins are not recognized even no EEPROM present. So, please note that processor only access DM9010BI after PWRST# deasserted 3ms. ...
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... T IOR# invalid to next IOR#/IOW# valid 6 When read DM9010BI register T2+T IOR# valid to next IOR#/IOW# valid 6 When read DM9010BI memory with F0h register T +T IOR# valid to next IOR#/IOW# valid 2 6 When read DM9010BI memory with F2h register T System Address(SA) valid to IO16,IO32 valid ...
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... T IOW# Invalid to next IOW#/IOR# valid 6 When write DM9010BI INDEX port T IOW# Invalid to next IOW#/IOR# valid 6 When write DM9010BI DATA port T +T IOW# valid to next IOW#/IOR# valid 2 6 When write DM9010BI memory T System Address(SA) valid to IO16, IO32 valid ...
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... RXCK RXER,RXDV RXD[3:0] Symbol RXER, RXDV,RXD[3：0] Setup Time RXER, RXDV,RXD[3：0] Hold Time 2 Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface ∫∫ → ← T1 ∫∫ Parameter ∫∫ → ← ...
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... MII Management Interface Timing MDC MDIO(drived by DM9010B) MDIO (drived by exetrnal MII) Symbol T MDC Frequency 1 T MDIO by DM9010BI Setup Time 2 T MDIO by DM9010BI Hold Time 3 T MDIO by External MII Setup Time 4 T MDIO by External MII Hold Time 5 10.3.9 EEPROM Interface Timing EECS EECK ...
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... Place the transformer as close as possible to the RJ-45 connector. Place all the 50Ω resistors as close as possible to the DM9010BI RXI± and TXO± pins. Traces routed from RXI± and TXO± to the transformer should run in close pairs directly to the transformer. The designer should be careful not to cross the transmit and receive pairs ...
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... Non HP Auto-MDIX Transformer Application ) Figure 11-2 Non HP Auto-MDIX Transformer Application Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface DM9010BI 53 ...
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... Power Decoupling Capacitors Davicom Semiconductor recommends placing all the decoupling capacitors for all power supply pins as close as possible to the power pads of the DM9010BI (The best placed distance is < 3mm from pin). The recommended decoupling capacitor is 0.1μF or 0.01μF, as required by the design layout. ...
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... EMI. Ground plane partitioning can cause increased EMI emissions that could make the network interface card not comply with specific FCC Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface regulations (part 15). Figure 11-4 shows a recommended ground layout scheme ...
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... Power Plane Partitioning The power planes should be approximately illustrated in Figure 11-5. Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Figure 11-5 Power Plane Partitioning DM9010BI 56 ...
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... A crystal can be used to generate the 25MHz reference clock instead of an oscillator. The crystal must be a fundamental type, and series-resonant. Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface qualify all magnetic specifications before using them in an application ...
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... Application of reverse MII Note: When operating DM9010BI at Reverse MII mode, pin 78 is pulled high. At this application, the txclk, col and crs pins will be changed from input to output. Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface ...
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... Dimension D & not include resin fins. 2. Dimension GD is for PC Board surface mount pad pitch design reference only. 3. All dimensions are based on metric system. Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface Unit: Inches/mm ...
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... Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function. Preliminary Version: DM9010BI--DS-P01 January 12, 2010 Industrial-temperature Single Chip Ethernet Controller with General Processor Interface application circuits illustrated in this document are for reference purposes only ...