L7C108 LODEV [LOGIC Devices Incorporated], L7C108 Datasheet - Page 14

• Manufacturer Part Number: L7C108
• Description: 128K x 8 Static RAM
• Manufacturer: LODEV [LOGIC Devices Incorporated]

1. Maximum Ratings indicate stress specifica-
tions only. Functional operation of these products
at values beyond those indicated in the Operat-
ing Conditions table is not implied. Exposure to
maximum rating conditions for extended periods
may affect reliability of the tested device.
2.
tion include internal circuitry designed to pro-
tect the chip from damaging substrate injection
currents and accumulations of static charge.
Nevertheless, conventional precautions should
be observed during storage, handling, and use
of these circuits in order to avoid exposure to
excessive electrical stress values.
3. This product provides hard clamping of tran-
sient undershoot. Input levels below ground will
be clamped beginning at –0.6 V. A current in
excess of 100 mA is required to reach –2.0 V.
The device can withstand indefinite operation
with inputs as low as –3 V subject only to power
dissipation and bond wire fusing constraints.
4. Tested with GND
disabled, i.e., CE
5. A series of normalized curves is available to
supply the designer with typical DC and
parametric information for Logic Devices Static
RAMs. These curves may be used to determine
device characteristics at various temperatures
and voltage levels.
6. Tested with all address and data inputs chang-
ing at the maximum cycle rate. The device is con-
tinuously enabled for reading, i.e., CE
Input pulse levels are 0 to 3.0 V.
7. Tested with outputs open and all address and
data inputs stable. The device is continuously
disabled, i.e., CE
8. Tested with outputs open and all address and
data inputs stable. The device is continuously
disabled, i.e. CE
levels are within 0.2 V of V
9. Data retention operation requires that V
never drop below 2.0V. CE
0.2 V or CE
must meet V
ensure full powerdown. For low power version if
applicable , this requirement applies only to CE
CE
and address.
10. These parameters are guaranteed but not
100% tested.
11. Test conditions assume input transition times
of less than 3 ns, reference levels of 1.5 V, output
LOGIC Devices Incorporated
V
N
2
IH
, and WE; there are no restrictions on data
The products described by this specifica-
, WE
OTES
2
V
IN
IH,
must be
with outputs disabled, OE
1
1
V
1
= V
CC
= V
V
IH
V
CC
- 0.2 V or V
OUT
, CE
CC
, CE
0.2 V. All other inputs
CC
, CE
2
2
1
or GND.
V
= GND.
must be
CC
2
www.logicdevices.com
V
IL
= GND. Input
. The device is
.
IN
1
V
0.2 V to
IL
V
, CE
CC
V
AC
CC
IH
1
2
-
.
,
loading for specified I
1a , and input pulse levels of 0 to 3.0 V Fig. 2 .
12. Each parameter is shown as a minimum or
maximum value. Input requirements are speci-
fied from the point of view of the external system
driving the chip. For example, t
as a minimum since the external system must
supply at least that much time to meet the worst-
case requirements of all parts. Responses from
the internal circuitry are specified from the point
of view of the device. Access time, for example,
is specified as a maximum since worst-case
operation of any device always provides data
within that time.
13. WE is high for the read cycle.
14. The chip is continuously selected CE
CE
15. All address lines are valid prior-to or coinci-
dent-with the CE
16. The internal write cycle of the memory is
defined by the overlap of CE
and WE low. All three signals must be active to
initiate a write. Any signal can terminate a write
by going inactive. The address, data, and control
input setup and hold times should be referenced
to the signal that becomes active last or becomes
inactive first.
17. If WE goes low before or concurrent with the
latter of CE
remains in a high impedance state.
18. If CE
current with WE going high, the output remains in
a high impedance state.
19. Powerup from I
of any of the following conditions:
a. Rising edge of CE
b. Falling edge of WE CE
c. Transition on any address line CE
d. Transition on any data line CE
The device automatically powers down from I
to I
conditions. This means that power dissipation is
dependent on only cycle rate, and is not on Chip
Select pulse width.
20. At any given temperature and voltage con-
dition, output disable time is less than output
enable time for any given device.
edge of CE
active .
2
WE active .
CC2
high .
after t
1
and CE
1
PD
1
and CE
has elapsed from any of the prior
CE
1
and CE
2
CC2
2
goes inactive before or con-
active .
OL
2
2
14
to I
CE
going active, the output
and I
2
CC1
1
1
transition to active.
, CE
active or the falling
O
1
H plus 30 pF Fig.
occurs as a result
AVEW
2
and CE
active .
1
, CE
is specified
1
, CE
2
, and
2
1
active
2
,
low,
CC1
PRELIMINARY INFORMATION
21. Transition is measured ±200 mV from steady
state voltage with specified loading in Fig. 1b.
This parameter is sampled and not 100% tested.
22. All address timings are referenced from the
last valid address line to the first transitioning
address line.
23. CE
address transitions.
24. This product is a very high speed device and
care must be taken during testing in order to real-
ize valid test information. Inadequate attention to
setups and procedures can cause a good part
to be rejected as faulty. Long high inductance
leads that cause supply bounce must be avoided
by bringing the V
up to the contactor fingers. A 0.01 μF high fre-
quency capacitor is also required between V
and ground. To avoid signal reflections, proper
terminations must be used.
Figure 1a.
Figure 2
Figure 1b.
OUTPUT
OUTPUT
GND
+3.0 V
+5 V
+5 V
<3 ns
1
, CE
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
10%
2
128K x 8 Static RAM
, or WE must be inactive during
CC
90%
and ground planes directly
Aug 11, 2010 LDS-L7C108/9-F
1M Static RAMs
R
R
5 pF
30 pF
1
1
480
480
L7C108
L7C109
90%
10%
R
255
R
255
<3 ns
2
2
CC