YMF744B ETC [List of Unclassifed Manufacturers], YMF744B Datasheet - Page 18

• Manufacturer Part Number: YMF744B
• Description: DS-1S
• Manufacturer: ETC [List of Unclassifed Manufacturers]

YMF744B
3Fh: Maximum Latency
40-41h: Legacy Audio Control
b[7:0] ..........Maximum Latency
b0................SBEN: Sound Blaster Enable
b1................FMEN: FM Synthesizer Enable
b2................GPEN: Gameport Enable
b3................MEN: MPU401 Enable
LAD
This register indicates how often DS-1S generates the Bus Master Request.
This register is hardwired to 19h.
This bit enables the mapping of the Sound Blaster Pro block in the I/O space specified by the SBIO bits,
when LAD is set to “0”. The FM Synthesizer registers can be accessed via SB I/O space, while the SB
block is enabled, even if FMEN is set to “0”.
This bit enables the mapping of the FM Synthesizer block in the I/O space specified by the FMIO bits,
when LAD is set to “0”. FM Synthesizer registers can be accessed via SB I/O space, while the SB block
is enabled, even if FMEN is set to “0”.
After setting FMEN to “1”, about 100 msec is necessary before accessing these I/O space.
This bit enables the mapping of the Joystick block in the I/O space specified by the JSIO bits, when LAD
is set to “0”.
This bit enables the mapping of the MPU401 block in the I/O space specified by the MPUIO bits, when
LAD is set to “0”.
b15
b7
“0”: Disable the mapping of the SB block to the I/O space
“1”: Enable the mapping of the SB block to the I/O space
“0”: Disable the mapping of the FM Synthesizer block to the FMIO space
“1”: Enable the mapping of the FM Synthesizer block to the FMIO space
“0”: Disable the mapping of the Joystick block
“1”: Enable the mapping of the Joystick block
“0”: Disable the mapping of the MPU401 block
“1”: Enable the mapping of the MPU401 block
Read Only
Default: 19h
Access Bus Width: 8, 16, 32-bit
Read / Write
Default: 907Fh
Access Bus Width: 8, 16, 32-bit
SIEN
b14
b6
b13
b5
Maximum Latency
MPUIRQ
b12
b4
b11
b3
b10
b2
SBIRQ
b1
b9
-18-
b0
b8
(default)
(default)
b7
SDMA
b6
(default)
I/O
b5
MIEN
(default)
b4
MEN GPEN FMEN SBEN
b3
February 3, 1999
b2
b1
b0