YMF744B ETC [List of Unclassifed Manufacturers], YMF744B Datasheet - Page 25

• Manufacturer Part Number: YMF744B
• Description: DS-1S
• Manufacturer: ETC [List of Unclassifed Manufacturers]

YMF744B
4E-4Fh: DS-1S Power Control 2
b0................CMCD: CODEC Master Clock Disable
b1................PSFM: Power Save FM Synthesizer
b2................PSSB: Power Save Sound Blaster
b3................PSMPU: Power Save MPU401
b4................PSJOY: Power Save Joystick
b5................PSPCA: Power Save PCI Audio
b6................PSSRC: Power Save SRC
Setting this bit to “1” disables the oscillation of the CMCLK. To stop a clock, when the CMCLK is
supplied to the AC’97, it is required that b13:PR5 bit of 4A-4Bh register is set to “1”. (If the Secondary
AC’97 is used, it is also necessary that b5:SPR5 bit of 5A-5Bh register is set to “1”.)
Setting this bit to “1” stops a clock supplied to the FM synthesizer block.
Setting this bit to “1” stops a clock supplied to the Sound Blaster block.
Setting this bit to “1” stops a clock supplied to the MPU401 block.
Setting this bit to “1” disables the comparator of the Joystick block.
Setting this bit to “1” stops a clock supplied to the PCI Audio block.
Setting this bit to “1” stops a clock supplied to the SRC block.
b15
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Disable
“0”: Normal
“1”: Disable
-
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b14
-
b13
-
PSHWV
b12
(default)
(default)
(default)
(default)
(default)
(default)
(default)
PSIO
b11
PSACL PSDIR
b10
b9
-25-
PSDIT
b8
PSZV PSSRC PSPCA PSJOY PSMPU PSSB
b7
b6
b5
b4
b3
February 3, 1999
b2
PSFM
b1
CMCD
b0