YMF744B ETC [List of Unclassifed Manufacturers], YMF744B Datasheet - Page 24

• Manufacturer Part Number: YMF744B
• Description: DS-1S
• Manufacturer: ETC [List of Unclassifed Manufacturers]

YMF744B
4C-4Dh: D-DMA Slave Configuration
b12..............PR4: AC’97 Power Down Control 4
b13..............PR5: AC’97 Power Down Control 5
b14..............PR6: AC’97 Power Down Control 6
b15..............PR7: AC’97 Power Down Control 7
Respective data set to b[15:8] are correspondingly set into the “Power down Control/Status” register in the
Primary AC’97 via the AC-Link. These are not set into the power down register in the Secondary AC’97.
b0................CE: Channel Enable
b[2:1] ..........TS: Transfer Size
b3................EA: Extended Address
b[15:4] ........Base Address : D-DMA Slave Base Address
This bit controls the power state of the AC-link in the Primary AC’97.
Setting this bit to “1” disables the internal clock of the Primary AC’97. In case the AC’97 is used with
DS-1S, the master clock is supplied from DS-1S. Therefore, when the clock is stopped completely, set
PR5 bits to “1” firstly, then the CMCD bit should be set to “1” after duration of 20µs or longer.
This bit controls PR6 bit status of the power control register in the Primary AC’97.
This bit controls PR7 bit status of the power control register in the Primary AC’97.
This bit enables the Distributed DMA function.
These bits indicate the size of the DMA transfer. Since DS-1S supports only 8-bit DMA transfer, the bits
are hardwired to 00b.
DS-1S does not support extended address mode. This bit is hardwired to 0b.
These bits indicate the D-DMA slave base address.
b15
“0”: Normal
“1”: Power down
“0”: Normal
“1”: Disable
“0”: Disable Distributed DMA
“1”: Enable Distributed DMA
Read / Write
Default: 0000h
Access Bus Width: 8, 16, 32-bit
b14
b13
b12
(default)
(default)
b11
Base Address
(default)
b10
b9
-24-
b8
b7
b6
b5
b4
EA
b3
February 3, 1999
b2
TS
b1
CE
b0