IC62LV256L ICSI [Integrated Circuit Solution Inc], IC62LV256L Datasheet - Page 2

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IC62LV256L

Manufacturer Part Number
IC62LV256L
Description
32K x 8 Low Power SRAM with 3.3V
Manufacturer
ICSI [Integrated Circuit Solution Inc]
Datasheet
IC62LV256L
FEATURES
• High-speed access time: 15, 20, 25 ns
• Automatic power-down when chip is deselected
• CMOS low power operation
• TTL compatible interface levels
• Single 3.3V power supply
• Fully static operation: no clock or refresh
• Three-state outputs
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
2
32K x 8 LOW VOLTAGE
CMOS STATIC RAM
— 255 mW (max.) operating
— 0.18 mW (max.) CMOS standby
required
FUNCTIONAL BLOCK DIAGRAM
I/O0-I/O7
A0-A14
GND
VCC
CE
OE
WE
DECODER
CIRCUIT
CONTROL
CIRCUIT
DATA
I/O
DESCRIPTION
The
32,768-word by 8-bit static RAM. It is fabricated using
high-performance CMOS technology. This highly reliable pro-
cess coupled with innovative circuit design techniques, yields
access times as fast as 15 ns maximum.
When CE is HIGH (deselected), the device assumes a standby
mode at which the power dissipation is reduced to
50 µW (typical) with CMOS input levels.
Easy memory expansion is provided by using an active LOW
Chip Enable (CE). The active LOW Write Enable (WE) controls
both writing and reading of the memory.
The IC62LV256L is available in the JEDEC standard 28-pin
300mil SOJ and the 8*13.4mm TSOP-1 package.
ICSI
IC62LV256L is a very high-speed, low power,
MEMORY ARRAY
COLUMN I/O
256 X 1024
Integrated Circuit Solution Inc.
ALSR008-0A 10/5/2001
ICSI
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