IC62LV256L ICSI [Integrated Circuit Solution Inc], IC62LV256L Datasheet - Page 5

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IC62LV256L

Manufacturer Part Number
IC62LV256L
Description
32K x 8 Low Power SRAM with 3.3V
Manufacturer
ICSI [Integrated Circuit Solution Inc]
Datasheet
IC62LV256L
READ CYCLE SWITCHING CHARACTERISTICS
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
2. Tested with the load in Figure 2. Transition is measured
3. Not 100% tested.
AC TEST CONDITIONS
AC TEST LOADS
Integrated Circuit Solution Inc.
ALSR008-0A 10/5/2001
Symbol
t
t
t
t
t
t
t
t
t
t
t
and output loading specified in Figure 1.
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
(3)
(3)
(2)
(2)
(2)
(2)
OUTPUT
3.3V
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE Access Time
OE Access Time
OE to Low-Z Output
OE to High-Z Output
CE to Low-Z Output
CE to High-Z Output
CE to Power-Up
CE to Power-Down
Including
jig and
scope
30 pF
Figure 1.
635 Ω
702 Ω
See Figures 1 and 2
0V to 3.0V
Min.
15
1.5V
2
0
3
0
Unit
3 ns
-15 ns
OUTPUT
±
Max.
500 mV from steady-state voltage. Not 100% tested.
15
15
15
7
8
6
3.3V
Including
(1)
jig and
scope
(Over Operating Range)
Figure 2.
5 pF
Min.
20
2
0
3
0
635 Ω
-20 ns
Max.
20
20
18
8
9
9
702 Ω
Min.
25
2
0
3
0
-25 ns
Max.
25
25
10
10
20
9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5

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