CH7013A-T ETC1 [List of Unclassifed Manufacturers], CH7013A-T Datasheet - Page 15

• Manufacturer Part Number: CH7013A-T
• Description: Digital PC to TV Encoder
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

CHRONTEL
Display Modes (continued)
proprietory Algorithms for enhancing the readability of text. These modes are fully programmable via the serial port
under the flicker filter register.
Internal Voltage Reference
An on-chip bandgap circuit is used in the DAC to generate a reference voltage which, in conjunction with a
reference resistor at pin RSET, and register controlled divider, sets the output ranges of the DACs. The CH7013A
bandgap reference voltage is 1.235 volts nominal for NTSC or PAL-M, or 1.317 volts nominal (for PAL or NTSC-
J), which is determined by IDF register bit 6 (DACG bit). The recommended value for the reference resistor RSET
is 360 ohms (though this may be adjusted in order to achieve a different output level). The gain setting for DAC
output is 1/48
I
For DACG=0, this is: I
For DACG=1, this is: I
Power Management
The CH7013A supports five operating states including Normal [On], Power Down, Full Power Down, S-Video Off,
and Composite Off to provide optimal power consumption for the application involved. Using the programmable
power down modes accessed over the serial port, the CH7013A may be placed in either Normal state, or any of the
four power managed states, as listed below (see “Power Management Register” under the Register Descriptions
section for programming information). To support power management, a TV sensing function (see “Connection
Detect Register” under the Register Descriptions section) is provided, which identifies whether a TV is connected to
either S-Video or composite. This sensing function can then be used to enter into the appropriate operating state
(e.g., if TV is sensed only on composite, the S-Video Off mode could be set by software).
Luminance and Chrominance Filter Options
The CH7013A contains a set of luminance filters to provide a controllable bandwidth output on both CVBS and S-
Video outputs. All values are completely programmable via the Video Bandwidth Register. For all graphs shown,
the horizontal axis is frequency in MHz, and the vertical axis is attenuation in dBs. The composite luminance and
chrominance video bandwidth output is shown in Table13.
201-0000-041
Table 12.Power Management
LSB
Operating State
Normal (On):
Power Down:
S-Video Off:
Composite Off:
Full Power Down:
= V(RSET)/RSET reference resistor * 1/GAIN
th
. Therefore, for each DAC, the current output per LSB step is determined by the following equation:
Rev. 1.0,
LSB
LSB
= 1.235/360 * 1/48 = 71.4 A (nominal)
= 1.317/360 * 1/48 = 76.2 A (nominal)
6/14/2000
Functional Description
In the normal operating state, all functions and pins are active
In the power-down state, most pins and circuitry are disabled.The
BCO pin will continue to provide either the VCO divided by K3, or
14.318 MHz out, and the P-OUT pin will continue to output a clock
reference.
Power is shut off to the unused DACs associated with S-Video
outputs.
In Composite-off state, power is shut off to the unused DAC
associated with CVBS output.
In this power-down state, all but the I
places the CH7013A in its lowest power consumption mode.
2
C circuits are disabled. This
CH7013A
15